Motorola Develops Copper/Low-k Technology
Peter Singer, Editor-in-Chief -- Semiconductor International, 7/1/1999
SESRC Launches
Copper IC Design Motorola
Develops 'The whole world is striving to get to higher performance
with lower-power parts. In going to increasingly lower dielectric constant
(low-k) materials, we're reducing the capacitance contribution to
resistance/capacitance delay,' said Fabio Pintchovski, vice president and
director of Motorola's Advanced Products Research and Development
Laboratory. 'This has the benefit of smaller signal propagation delays,
less cross talk between adjacent lines and reduced power consumption. In
our solution, Motorola has discovered an optimal choice of an integration
scheme to support bringing copper and porous low-k materials together
successfully for advanced interconnects.'
In its efforts to drive the availability and application
of this process technology, Motorola was the first company to demonstrate
the multilevel integration of porous low-k and copper with parametrics on
par with copper and SiO2, as revealed at the spring meeting of
the Materials Research Society.
Motorola's solution uses porous low-k materials with k
values between 2.0 and 2.5. By contrast, SiO2 has a k value of
3.9-4.2. Also, since stress migration behavior is a critical reliability
indicator for new materials and processing, it is significant that the
stressing of the copper and porous low-k structures resulted in
equivalency with copper and SiO2-stressed parts.
Challenge
The Semiconductor Research Corp.,
Novellus Systems Inc., the UMC Group and SpeedFam/IPEC are sponsoring a
university design contest with $150,000 in cash prizes and $850,000 in services.
The contest objective is to create novel circuit designs by engaging the
creative interests of university faculty and students.
Copper/Low-k Technology
For the
first time, a major device manufacturer has created a technology solution
that integrates copper with porous low-k dielectric films. This
achievement by Motorola will help reduce capacitance in integrated
circuits yielding an improvement in on-chip speed.
'We are excited about this contest,' said Dr. Karey Holland, vice president and chief technical officer for SpeedFam-IPEC, 'because it will serve to further promote the proliferation of copper interconnect development. We applaud SRC, Novellus and the UMC Group for their foresightedness in issuing this design challenge to the university community.'
Contestants will design a circuit or circuit subsystem (clock network, analog
building block, etc.) that uses the enhanced properties of the Cu interconnect
technology to achieve significant functional or performance gains over the same
circuit built with traditional aluminum interconnect technology. Sponsors are
looking for creativity, unanticipated innovations, and the best use of the
emerging technology. Top contestants will have the opportunity to access design
technology at UMC Group foundry.
Hitachi
Enters into Joint 300 mm Research
Programs with International
SEMATECH
Hitachi Ltd. (Tokyo) and International SEMATECH (Austin, Texas) announced a joint program involving the implementation of five systems, several of which will be 'bridge' tools for both 200 mm and 300 mm processes.
The program, designed to be approximately 27 months in duration, is scheduled to begin in July. This agreement is designed to create 130 nm and 100 nm test material for member companies, accelerate Hitachi's 300 mm technologies and assist other equipment suppliers in advanced tool development.
Under the terms of the agreement, the following systems are involved:
- 300 mm Etching system configured to support both Gate and Dielectric Etch processing to be delivered with a 200 mm bridge kit.
- S-9300 CD-SEM, which is both 200 mm and 300 mm capable for measuring fine pattern geometries.
- WI-1100 Automatic Wafer Inspection System for detecting defects on patterned silicon wafers also capable of 200 mm and 300 mm operation.
- OSDA Optical Shallow Defect Analyzer for detecting and measuring crystal defects in the silicon wafer surface layer in a high throughput and non-destructive manner.
- SCDS Catalytic Decomposition system for abatement of PFC, HAP, etch, CVD and TEOS gases.
For information on Hitachi etchers and gas abatement systems, visit www.hitachi.com/semiequipment. For more information on Hitachi instrument and measurement products, visit www.nissei.com.
International SEMATECH is a wholly owned subsidiary of SEMATECH, which
includes SEMATECH members and Hyundai, Infineon (Siemens), Philips, ST
Microelectronics and TSMC. Additional information about the consortia can be
found on the Internet at http://www.sematech.org/. 
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