Failure Analysis Preparation: A System Assessment

Laurent Bellon, Phillippe Sardin, Nadine Bicais-Lepinay, Luc Decroix -- Semiconductor International, 7/1/1999

Failure analysis on packaged dies and wafers is extremely important for semiconductor manufacturers. Each new chip prototype is not always fully functional and may diverge from initial target specifications. Failure analysis locates specific failure sites and determines if a design mistake, process problem, material defect or some type of induced damage caused it. Feedback of this information to the design and process groups minimizes expensive design iterations, photo mask modifications and processing cycles -- and reduces the time-to-market and improves production yields.

Failure analysis is also used on field returns to assess defects and allow for corrective actions to improve product lifetime.

To prepare samples for analysis, the failure analyst is often called to deprocess devices (remove passivation layers) while still maintaining the full electrical functionality of the circuitry for further testing.

A recent European SEA (Semiconductor Equipment Assessment) project evaluated etch process capabilities of the Nextral 860 high- density plasma etcher, developed specifically for failure analysis (FA) sample preparation. The FANETA (Failure Analysis Plasma Etch Equipment Assessment) program was carried out over 12 months at Alcatel Microelectronics in Oudenaarde, Belgium. Other industrial evaluators were ST Microelectronics in Crolles, France and Siemens in Munich, Germany.

Fig. 1 E-beam voltage contrast imaging is an essential part of design debugging. The image shown is free from charging effects.

Fig. 2 This image, obtained with a focused ion beam too, shows a deprocessed five metal-level packaged die. A CHF3/C2F6 chemistry was used in the deprocessing step.

Fig. 3 The etch rate of Si02 is shown as a function of the dc bias and pressure with constant uhf power at 1200 W.

The FANETA project evaluation focused on the following capabilities of the Nextral 860:

• Clean anisotropic depassivation down to five metal layers on packaged dies while maintaining the full functionality of the product
• Reverse engineering of 6 in. and 8 in. wafers for deep-submicron technologies with geometries #O.25 µm and up to six metal layers
• Thick silicon thinning of the backside of packaged dies for light emission microscopy and IR inspection
• Selective deprocessing of packaged dies for failure analysis

Experimental setup

The Nextral 860 chamber consists of these interconnected elements:

• An UHF power source that produces a constant frequency (2.54 GHz)
• A waveguide to transmit the microwave power to the process chamber
• A cavity where a plasma is created by a surface wave (standing wave around the process chamber)
• The microwave plasma load for UHF power source protection against excessive reflected UHF power.

The energy is periodically distributed in the cavity around the process chamber. A standing wave system is developed and electromagnetic energy is stored within the cavity. The matching device, used to optimize energy coupling, has a unique, predetermined adjustment for a given range of UHF power, pressure and gases used. This ensures matching for plasma discharges operating with different process parameters.

The surface wave system gives rise to a plasma electronic density > 5 x 10¹¹ electrons per cubic centimeter. With the energy levels used in HDP, a high density of reactive species is created by the electrons, leading to higher etch rates. In addition, the plasma potential can be very low, particularly with processes of working pressures above 15 mTorr (does not exceed 20 Volts). Consequently, no damage from high-energy ion bombardment can occur on the substrates.

With this configuration, the substrate holder can be either floating or connected to an additional rf generator when rf polarization is needed for bias monitoring.

Process optimization was carried out using Design of Experiments (DOE) software to enhance etch rates, etch uniformity and cleanliness, while reducing metal erosion and maintaining electrical functionality of the devices.

Deprocessing of packaged die

The main need for depassivation and removal of intermetal dielectrics on packaged dies is for design debugging of prototypes on multi-level metal technologies using e-beam voltage contrast testing. This entails uncovering four to five levels of metal, while maintaining the chip's electrical functionality. The voltage contrast imaging must also give suitable results for the e-beam analysis: no dramatic charge-up after a few minutes of probing and a clean surface for good image resolution.

Fig. 4 Cleanliness versus bias and pressure with constant UHF power of 1200 W is depicted.

Three processes were evaluated and optimized during this phase of the project using 1) CHF₃, 2) CHF₃ and C₂F₆, and 3) C₂F₆. ST Microelectronics and Siemens analyzed the results. The goal was to maintain the parametric values of electrical continuity and circuit functionality down to Metal 1 on five metal-layer packaged dies.

A gas mixture of argon and CHF₃ with a working pressure of 20 mTorr produced a SiO₂ etch rate of 100 nm/min and electrical functionality down to Metal 1. Figure 1 shows the e-beam voltage contrast image with no charging effect.

This CHF₃ and C₂F₆ process recipe was tweaked to obtain less metal line erosion and a faster etch rate. The final recipe used a gas mixture of CHF₃ and C₂F₆ with a working pressure of 20 mT using HDP and RF biasing. A 2-min. post discharge treatment was used with argon and oxygen. An SiO₂ etch rate of 150 nm/min was obtained. Figure 2 shows an FIB photo of the deprocessed five metal-level packaged die using this recipe.

The C₂F₆ process recipe was developed and tested by Siemens on 8-in. and 6 in. wafers, pieces of wafers as well as packaged dies. The recipe uses a gas mixture of C₂F₆ and argon using HDP and RF biasing. The achieved SiO₂ etch rate was significantly higher (250 nm/min). All three processes were retained as excellent deprocessing solutions since cleanliness was achieved and electrical functionality maintained.

Fig. 5 Metal erosion was clearly avoided when using lower UHF power during deprocessing.

Reverse engineering of full wafers

ST Microelectronics supplied the 8- in. wafers and Alcatel Microelectronics supplied the 6 in. wafers used for this extensive evaluation. Each group analyzed the wafers following each design step. The devices on the 8 in. wafers were a five metal-level technology and deprocessing with high-density plasma (HDP) was performed down to the first level of metal.

The gas flow (argon and CHF₃) and helium pressure were kept constant, Variable parameters used to optimize the process were the working pressure, dc bias voltage and the microwave (UHF) power. Control of the temperature by helium cooling was vital to maintain the electrical functionality of the devices. Figure 3 illustrates the etch rate of SiO₂ on the full wafers as a function of the dc bias and working pressure with constant UHF power of 1200 W. The etch cleanliness of the surface after etching was evaluated on a scale of 0 to 100 (0 being very unclean and 100 very clean). Cleanliness versus bias and pressure with constant UHF power of 1200 W is depicted in Figure 4.

It was important to avoid metal erosion in order to allow extensive analysis of the metal lines following deprocessing. The UHF power was varied between 1200 and 1600 W under constant working pressure and self-bias. Metal erosion increased significantly as UHF power increased. Figure 5 shows an 8 in. wafer sample processed at 1200 W. Metal erosion was clearly avoided when using lower UHF power during deprocessing.

Metal erosion and cleanliness of the wafer was also evaluated while keeping the UHF constant (1200 W) and changing the self-bias voltage. At 15 V, there was virtually no metal erosion observed and the wafer was clean (again seen in Fig. 5). As self-bias increased up to 50 V, both metal erosion and 'grass' formation increased. 'Grass' formation on the device is a redeposition of material on the surface, making further analysis of the circuit visually and electrically difficult due to short circuits between interconnect levels.

Fig. 6 After HDP etching, no damage is seen to the metal lines or sidewalls.

Fig. 7 An image is recorded before backside thinning.

Fig. 8 After removing 300 microns of silicon, a new image is otained.

The last parameter checked in the experiments was the effect of pressure. At a working pressure of 27.5 mTorr (with self-bias at 15 V and UHF power at 1200 W) the end result was perfectly clean (Fig. 5). Grass formation slightly increased with the increase of pressure up to 40 mT. However, less metal line erosion was observed at higher pressure. The final optimized processes were then tested with real FA applications allowing the full evaluation of the results.

Accurate location of vias

To accurately locate vias, it was necessary to remove passivation down to metal 4 using a clean and uniform process and precise end- point detection. The chosen process used a 27.5 mT working pressure, 15 V self-bias and 1200 W UHF power.

Observation of stress voiding

This application required no erosion on the top metal levels and no sidewalls following deprocessing for the metal lines to be accurately observed. This time, a higher working pressure was used (40 mT) with 15 V bias and 1200 W UHF power again. Figure 6 shows the result with undamaged metal lines and no sidewalls after HDP etching.

Determine cause of shorts at metal 1

The criteria for this application was very clean etching down to metal 1 with good selectivity against TiN. The same process as for application 1 was used and due to the cleanliness and high selectivity to TiN, enabled identifying and observing good and bad zones on the same die.

Backside silicon thinning on packaged dies

The evaluation of the silicon backside thinning process had two main steps involving feedback from all the project partners. First, an image was recorded before thinning the silicon (Fig. 7). There was good image contrast and resolution, but with poor signal intensity with a well-defined emission spot. Following the removal of 300 microns of silicon, the image was compared (Fig 8). The thinning of silicon enabled a good image as well as good signal intensity. However, the emission spot location was less defined due to a rougher surface. Another experiment was carried out by stripping off all the silicon from the backside of the die using a process with high selectivity to oxide. In this case, the information for analysis was available on large areas at lower metal levels (Fig. 9).

Fig. 9 Stripping all silicon from the backside of the die allowed large areas of lower metal levels.

Conclusion

The 12-month SEA program allowed cooperation among the industrial evaluators: Alcatel Microelectronics, ST Microelectronics, Siemens and the equipment manufacturer, BPS-Nextral. The extensive evaluation proved the equipment was able to meet the high requirements of mainstream IC manufacturers. The feedback from the partners enabled further process optimization, which, in turn, benefited those partners involved in the FANETA project.

Suggested Additional Reading

1. Weiss, M., 'Overall Factory Effectiveness (OFE) and its Implications for 300 mm Tool Automation,' Semiconductor Fabtech, Fifth Edition, p. 57.
2. Weiss, M., 'Using Analytical Methods to Accelerate Material Handling System Design Optimization,' SEMI Taiwan Technical Symposium, September 1995.
3. VanLeeuwen, C., 'Implications of 300 mm for Fab Design and Automation,' Semiconductor International, April 1996.
4. I300I Guidelines on 300 mm Process Tool Mechanical Interfaces for Wafer Lot Delivery, Buffering and Loading (Rev D. 9/3/96).
5. 2nd Lecture, IC's Factory Design for 300 mm Wafer Line Standardizing Study, Japan 300 mm Semiconductor Technology Conference (J300), Dec. 3, 1996.
6. Plata, J.J., '300 mm Fab Design, A Total Factory Perspective,' IEEE 6th International Symposium on Semiconductor Manufacturing, San Francisco, Calif., October 1997.
7. Subramanian, B., Kryder, K. D., 'Automation Challenges in the Next Generation Semiconductor Factory,' Semiconductor Fabtech, 7th Edition, ICG Publishing.
8. Griessing, J., Ortner, J., 'Sea of Lots Concept,' European Semiconductor, September 1997.

	Laurent Bellon received a degree in electrical engineering from the Institut en Sciences et Technologies, Paris (France). In 1996, he joined BPS-Nextral, Montbonnot (France), where he is in charge of the design of plasma chambers.
	Philippe Sardin graduated with a degree in microelectronics from the University of Bordeaux, Laboratorie IXL, France, in 1991. He joined ST Microelectronics at the Crolles plant in 1994 as a test engineer and is in charge of developing failure analysis for Central R&D prototype circuits.
	Nadine Bicais-Lepinay has a degree in physical measurements and has worked for IBM. She joined ST Microelectronics in 1994 and is currently responsible for a Failure Analysis group in Crolles as a physical characterization engineer.
	Luc Decroix received a B.S. degree in electrical engineering from the Provinciale Industriele Hogeschool West Vlaanderen, Kortijk, Belgium. He has worked at Alcatel Microelectronics since 1993. In 1997, he joined the Central Service Laboratory where he is responsible for the analysis of failures.
	Rainer Weiland received his diploma and his Ph.D. in chemistry from the University of Kaiserslautern, Germany, in 1977 and 1983, respectively. He joined Siemens in 1986 and is currently senior manager of the Physical Failure Analysis Department of the Infineon Technologies AG.