Gas Dome Dielectric System Provides Unity-k Dielectric

Thomas E. Wade, Ph.D.,
University of South Florida., Tampa, Florida -- Semiconductor International, 7/1/1999

The RC delay associated with interconnect is rapidly becoming the limiting factor in realizing high-speed integrated circuits with design rules below 250 nm (0.25 µm).¹ As packing density increases, the cross-sectional area of interconnect lines decreases causing the resistance-to-length ratio to dramatically increase. The adoption of copper as the conductor of choice can improve the resistance component by almost a factor of two over that of aluminum (from 3.0 µ+-cm to 1.7 µ+-cm resistivity). A dramatic reduction in the dielectric constant of the intermetal dielectric material over that of silicon dioxide (k = 4.1) is also needed to address the capacitance component for future high-speed circuitry.

A reduction in interconnect line capacitance can reduce signal propagation delay, power consumption at high frequencies and cross coupling between conductors (cross-talk and noise). Another significant benefit of reducing RC delay is the reduction of process complexity. A 130 nm (0.13 µm) design would require 12 levels of metal in an Al/SiO₂ system, but only six levels of metal using Cu/low-k system. This simplification improves reliability and yield while reducing cost.

A reduction of wire capacitance can also provide an increased degree of design freedom. The designer can use the reduction in capacitance to either improve speed or reduce power.²

Fig. 1 The 'gas dome dielectric system' (GDDS) uses an oxide dome to contain a gas dielectric. Thick metal towers and oxide supports for metal traces and bond pads complete the system.

There is a wide variety of organic and inorganic materials currently under investigation as potential candidates for low-k intermetal dielectrics.³ Also, procedures have been proposed to conduct comparative evaluations of these candidates to find the optimal material.⁴ Many of these candidates exhibit severe reliability, manufacturability and/or process integration problems, especially the organic candidates.

Properties required for an acceptable intermetal dielectric material include low dielectric constant (ideally k = 1.0); high breakdown field strength (>2 MV/cm); low bulk leakage (resistivity > 10¹⁵ +cm); low surface conductance (surface resistivity > 10¹⁵ +); low stress (compressive or weak tensile > 30 MPa); mechanical, chemical and thermal stability; no moisture absorption or permeability to moisture; process compatibility (CMP/dual damascene/etc.); good thermal properties (high thermal conductivity and low coefficient of thermal expansion) and compatibility with environment, health and safety requirements.

The National Technology Roadmap for Semiconductors calls for dielectrics with k = 2.5 - 3.0 for 180 nm (0.18 µm) devices and 2.0 - 2.5 for 150 nm (0.15 µm) devices.¹ If a reliable unity-k dielectric system could be realized using conventional technological processes, a quantum step towards meet-ing Roadmap goals could be achieved (Fig. 1).

Fig. 2 One possible process for realizing a GDDS is: a) Deposit, pattern and hard mask pre-metal oxide. b) Etch dielectric to M1 depth. c) Deposit low Tg polymer and planarize. d) Dual damascene etch of dielectrics. e) Deposit metal and planarize. f) Deposit etch-stop and second-level oxide. g) Etch thick oxide using PR mask. h) Etch remaining oxide to M2 depth using hard mask. i) Remove etch-stop layer, deposit and pattern low Tg polymer, deposit second-level metal, planarize and deposit another etch-stop layer. j) Repeat for the third-level metal.

The concept of using air, vacuum or gas as an intermetal dielectric is not new.^5-7 Air gaps formed between metal lines during SiO₂ deposition reduce the intralevel dielectric capacitance by as much as 40%, yielding a net line capacitance reduction of over 20%.

Also, theoretical and experimental evaluations of air gap samples demonstrate that the electrical (leakage current), re-liability (electromigration) and thermal properties are comparable with those associated with HDPCVD SiO₂ and HSQ materials.⁷ Damascene metal processes that incorporate air gaps have yet to be demonstrated.

Gas dielectrics offer many benefits as delineated in Table 1, the most significant being reduced cost, improved yield and higher speed circuitry. In general, unity-k dielectrics provide the most benefit where lines are at their minimum pitch.

Gas dome dielectric system (GDDS)

The proposed gas dome dielectric system (GDDS) consists of a SiO₂ dome and a gas dielectric for the metal conductors underneath (Fig. 1). The dome may be a 'partial' dome, covering only the lower level conductors, or it can be a 'full' dome where all metal levels are embedded in the gas dielectric. For purposes of process integration, reliability and thermal conductivity, the partial dome concept will be demonstrated.

If conductors are embedded in a gas, they must be supported to maintain structural integrity. The conductors can be held in place using inorganic insulating supports and braces (i.e., SiO₂) as illustrated in Figure 1. Properly designed, these conductors can be structurally sound without the need of continuous underlying support. To add strength to the conductor runs, a thin stiffening material layer can be deposited on either the bottom or top side of the conductor.

Process flow

One possible process flow is illustrated in Figure 2. Starting with a processed silicon wafer, a thick premetal dielectric (typically HDPCVD SiO₂) is deposited and a silicon nitride hard mask is patterned on it (2a). The premetal dielectric is etched to a depth equal to the desired thickness of the first level metal and filled with a low T_g polymer (2b & 2c). After curing the polymer and planarizing, a dual damascene etch is performed to delineate first-level metal trenches and contact holes to the silicon surface (2d). Next, first-level metal is deposited that incorporates the appropriate liner/barrier layer, seed layer and final bulk layer, followed by CMP planarization (2e).

To start the next level, a thin etch stop layer, typically silicon nitride, is deposited followed by the deposition of a thick oxide layer (e.g., HDPCVD SiO₂) (2f). This oxide layer is then patterned with a photoresist mask (2g) and then with a hard mask (2h). Next, the exposed thin etch stop layer is removed, followed by the deposition of the low T_g polymer material. The polymer is then patterned for second-level metal trenches and vias, and the second-level metal is deposited and planarized (2i). The same processing steps are followed in depositing the third-level metal (2j).

 

Fig. 3 A thin etch-stop is deposited followed by a thick high-integrity oxide 'dome.' Vias are etched in the dome and filled with metal. Large metal 'vapor blocks' are made as a part of the preceding process.	Fig. 4 A 'vapor port' is etched in the dome directly above the metal vapor block, and the system is heated from the top to vaporize the polymer in the presence of a vacuum.

The next step is to deposit a thin etch-stop layer followed by a very thick and dense oxide layer, which will act as the 'dome' for all underlying layers (Fig. 3). Vias through the dome are etched, filled with metal and the metal is planarized. In the process of building up the various metal layers and vias, large metal 'vapor block' structures are realized. This metal vapor block has multiple purposes, as will be shown.

Fig. 5 One way to close the vapor port after backfilling is to: a) Deposit a thick metal that partially fills the vapor port. b) 'Spot weld'the metal layer after backfilling.

The next step is to etch large 'vapor ports' in the dome layer directly above the metal vapor blocks all the way down to the low T_g polymer material (Fig. 4). In the presence of a vacuum, this structure is next heated from the top side, possibly with quartz lamps or some other thermal processing equipment, to a temperature far exceeding the T_g temperature of the polymer material. This causes the polymer to ash and vaporize through the vapor ports. Applying heat to the top side of the wafer causes the metal vapor block to heat up first, thus vaporizing the polymer around it. Since the dome layer heats faster than the silicon substrate, the top polymer layers will tend to vaporize before the lower layers, resulting in an orderly vaporization of all the polymer material.

The next step is to back-fill the underlying dome area with the desired 'dielectric' gas and close the vapor port. For thermal conduction purposes, light molecular gases like hydrogen or helium are the most desirable. One possible backfilling process is illustrated in Figure 5a where a thick metal layer is deposited under vacuum on top of the dome layer, the thickness selected to almost completely fill the vapor port. The vacuum chamber is then filled with the dielectric gas. The metal around each vapor port is then spot welded, possibly with a laser, to cause the metal to flow into the port to close it (Fig. 5b). With the gas trapped, complete filling of the vapor port and planarization can be accomplished (Fig. 6).

Thermal conduction

The biggest disadvantage of using gas dielectrics is their poor thermal conductivity. Increased temperatures in the interconnect stack, due to Joule heating, can result in reliability problems, including enhanced electromigration. In gases, heat is conducted by the molecules themselves, so gases with lighter and faster molecules, like helium, are better heat conductors than heavier gases, like nitrogen or air. Obviously, the more concentrated the gas, the better the thermal conductivity.

Table 2 gives the thermal conductivity of various materials at room temperature. As seen from this data, the thermal conductivity of light gases is comparable to that of polymers like polyimide. In fact, numerical simulations involving air-gap interconnect systems show that temperature rises are only slightly higher than those for homogeneous SiO₂ dielectrics and are actually lower than for homogeneous low-k materials.⁷ However, these systems did not have the conductor completely surrounded with a gas, where heat is transferred only by convection.

To extract heat from the gas dome system, high thermal conduction paths must be introduced in the form of metal columns where possible. This is another possible use for the metal vapor blocks. It is also possible to introduce metal in portions of the dome layer away from vias and other features to assist in removing heat.

Fig. 6 The vapor port is completely filled and planarized after the dome is sealed.

One last challenge exists in providing structural integrity for contacts and bonding pads. Just as large metal vapor block structures can be realized as the metal layers are built up, it is possible to realize large SiO₂ dielectric block structures from the bottom to the top of the dome structure. These dielectric block structures can provide added structural integrity to the dome, over which bonding pads can be placed.

Conclusions

A unity-k gas dome dielectric system (GDDS) is proposed that uses a light molecular gas having good electrical properties for its interlayer and intralayer dielectric material. The proposed processing scheme utilizes only current technologies and, therefore, should be realizable. The final structure incorporates only high conductivity metal (Cu or Al) and widely used inorganic dielectrics materials (silicon oxides/nitrides), eliminating the reliability issues associated with most low-k materials. Thermal conductance issues for the gas dome region require special attention, but they should be comparable with those of most current low-k polymer materials, especially the nano-pore materials.

Table 1 Benefits Of Gas Dielectrics Optimal Electrical Properties Unity dielectric constant (k = 1) High breakdown strength Low leakage High volume and surface resistivity No polarization effects (dipole moments) Low ionic/contamination/migration/mobile ion/charge trapping effects Optimal Mechanical Properties No shrinkage No thermal or intrinsic stress (pinhole density/ particulates No problems with adhesion /cracks & seams/etch pits/etc.) No planarization problems No defect density issues No gap fill problems Optimal Chemical Properties Resistant to corrosion, leaching and precipitation No EHS issues Optimal Design/Processing Characteristics Scalability Reduced complexity and cost/improve yield Barriers needed only for processing Reduced overall cost-of-ownership Commercially available sub-processes

Table 2 Thermal Conductivities of Various Metals Material/Metals Thermal Conductivity W/cm-K Silver 4.3 Copper 4.0 Aluminium 2.3 Molybdenum 1.4 Semiconductors   Silicon 1.5 Germanium 0.7 Gallium Arsenide 0.5 Insulators   Alumina (Al2O3) 0.2 Silicon Dioxide (Si02) 0.001 Polymide 0.004 Epoxy Glass (PC Board) 0.003 Gases   Hydrogen 0.001 Helium 0.001 Oxygen 0.0002 Air 0.0002

This article was adapted from a luncheon presentation given at the Fifth International Dielectrics for ULSI Multilevel Interconnection Conference (DUMIC) held February 8-9, 1999 in Santa Clara, California.

References

1. National Technology Roadmap for Semiconductors: Technology Needs. Published by Semiconductor Industry Assoc., pp. 99 - 110, 1997.
2. G.A. Sai-Halasz, Proc IEEE, Vol. 83, No. 1, p. 20, 1995.
3. D.S. Armbrust and D. Kumar, Short Course on Dielectrics for ULSI Multilevel Interconnection Visuals Booklet, DUMIC, Santa Clara, Calif., Feb. 10, 1999.
4. T. E. Wade, 'Optimum Dielectric Selection Using a Weighted Evaluation Factor,' DUMIC, pp. 211 - 218, 1995 and Semiconductor International, pp. 99 - 106, Vol. 38, No. 8, Aug., 1995.
5. J.G. Fleming and E. Roherty-Osmum, 'Use of Air-Gap Structures to Lower Intralevel Capacitance,' DUMIC, pp. 139 - 145, 1997.
6. M.B. Anand, M. Yamada and H. Shibata, 'Use of Gas as Low-k Interlayer Dielectric in LSI's: Demonstration of Feasibility,' IEEE Trans. on Electron Devices, Vol. 44, No. 11, pp. 1965, 1997. 7. B. Shieh, K. Saraswat, M. Deal and J. McVittie, 'Air Gaps Lower k of Interconnect Dielectrics,' Solid State Technology, Vol. 42, No. 2, pp. 51 - 58, Feb., 1999.
7. B. Shieh, K. Saraswat, M. Deal and J. McVittie, 'Air Gaps Lower k of Interconnect Dielectrics,' Solid State Technolgy, Vol. 42, No. 2, pp. 51-58, Feb., 1999.

Thomas E. Wade received his Ph.D. from the University of Florida in 1974. He is currently at the University of South Florida where he has served as Professor of Electrical Engineering and Associate Dean for Research. He has been involved with on-chip multilevel interconnection research since the late 1970's, and has been the General Chairman of the International VLSI Multilevel Interconnection Conference (VMIC) since it started in 1984.

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