Enabling Technologies Prevail at SEMICON West 99
SI Editors -- Semiconductor International, 7/1/1999
Enabling technologies always steal the headlines in this industry, but that is especially true during times of recovery when the only purchases made are those that enable a new processing capability, higher throughput or lower cost. This year, the editors of Semiconductor International expect to see enabling technologies in all process areas to extend optical lithography and develop processes for copper and low-k dielectrics including etching, polishing, ashing, etc. Emphasis on metrology and yield management increases in the sub-0.25 µm regime. Assembly and packaging area promises new developments to accelerate high-performance operation.
Advanced lithography
For the past year, the extension of optical lithography has been a topic of much discussion. At SEMICON West 1998, there was little talk of 157 nm lithography; it was not on any industry roadmap. But by March of this year, 157 nm was hot. As International SEMATECH narrowed the possible successors to optical lithography to two, SCALPEL and EUV, virtually every stepper company was studying 157 nm. One potential roadblock has been the lens mater-ial, CaF2, a soft material prone to chipping. However, companies such as SVGL believe they have a handle on this technology.
With continued device geometry shrinks, a phenomenon called the Mask CD deviation Enhancement Factor (MEF) becomes a growing concern. When the k1 factor, a measure of the degree
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| Fig 1 By measuring and eliminating systematic manufacturing errors, new overlay reticles can improve matching performance between steppers and scanners. (Source: ASML) |
Resolution enhancement technologies (RET) such as alternating phase-shift masks (PSMs) could abate MEF. In this case, RETs increase depth of focus and exposure latitude and reduce MEF. However, other RETs, such as optical proximity correction (OPC), may exacerbate MEF. Understanding the interaction of the diffraction orders with the lens and illumination provides insight to MEF's impact. While these issues are being studied, new PSM designs and software to implement them have been introduced, and resists are being developed to extend the linear region. But to some, a more practical approach to resolving MEF issues is a move to 6X or even 8X reticles.
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| Fig 2 REZI-28 aqueous residue remover specifically targets organometallic and inorganic residues left after ashing. (Source: J.T. Baker) |
Wafer processing trends
The delayed transition to 300 mm wafer processing continues to be a focus of semiconductor manufacturing equipment development. Most new tools are 'bridge' tools, designed to address both 200 mm and 300 mm requirements. However, it is unclear when the industry will move to 300 mm processing and whether today's technologies will then be adequate.
The other critical wafer processing change underway is the move from the aluminum/SiO2 interconnect strategy to a copper/low-k approach. Presently, several companies -- most notably IBM and Motorola -- are using copper for all metal levels. Others use copper only for the top levels where most of the power is carried. The industry appears to have agreed on how to process copper, using a dual damascene technique for patterning, followed by the deposition of a Ta or TaN diffusion barrier, Cu seed layer (by PVD), electroplating (also called electrochemical deposition) the bulk of the Cu and Cu planarization by CMP.
The low-k dielectric picture is much less clear. A fluorinated silicate glass (FSG) is used in production, sometimes touted as a 'low-k' material. However, FSG only offers a slightly lower k of 3.5, compared to a k of 3.9 for SiO2. Achieving true low-k in the mid-2 range (or lower) requires going to new material. Over a dozen different low-k candidates are offered, many with reasonable thermal stability and good mechanical and electrical properties. But a clear winner has yet to emerge. Low-k materials, whose porosity can be increased to lower k value, may hold the greatest potential -- making it possible to adopt a low porosity version for early generation devices, using a higher porosity material for subsequent generations.
In the front-end of the line, traditional ion implantation techniques will continue to be used for at least the next two device generations, challenged only by the need to create very shallow source/ drain junctions. After that, it may be necessary to go to an alternative doping strategy, such as PIII (plasma immersion ion implantation), GILD (gas immersion laser doping) or PLAD (plasma assisted doping). As voltage levels drop (from 3.3 to 1.8 V), the gate oxide will become thinner to maintain an acceptable drive current (Id). The gate oxide must also be a good diffusion barrier, calling for oxynitride and stacked gate dielectrics. Eventually, high-k dielectrics will be used for the gate oxide, again, to optimize drain current. At the contact level, cobalt silicides are gradually replacing titanium silicides. Tungsten continues to provide contact metal-1 with the source, drain and gate.
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| Fig 3 The Stylus NanoProfilometer CD-metrology tool evaluates focus/exposure matrix arrays for photomasks stepper characterization. (Source: Surface/Interface Inc.) |
Clean processing
The challenges of 0.25 µm and 0.18 µm manufacturing drive tighter control of contaminants and defect management in the fab. In every aspect of gas and liquid delivery, engineers seek long-term solutions for improved contamination control and more reliable systems. For instance, DI water systems must produce water of acceptable purity and resistivity, while doing so hour-to-hour, day-to-day and month-after-month. With accelerated shrinks, the system requirements must follow aggressive roadmaps to maintain high yields.
A number of enabling solutions in wafer cleaning and drying are coming about with the move from Al/SiO2 to Cu/low-k dielectric interconnect processing. The risk of copper contamination is of utmost concern in wet processing steps, causing segregation of tools for at least the first generation of copper interconnects. Removal of contaminants, especially polymer-based, is requiring new non-dry but also non-wet processes using cryogenics and other means to clean wafer surfaces. Likewise, ashing and etching processes are using new chemistries for, for instance, removal of photoresist from low-k materials following etching to create vias in damascene structures. The mix of wet/dry processing is bound to change in the future.The delay of 300 mm is buying the industry time to truly optimize 300 mm fabs for high-productivity, reduced-cost operation.
Inspection, measurement and testing
For years, precision, not accuracy, was a primary consideration of process control metrology tools. With the accelerated progression to smaller architectures at a rate of three shrinks per year, precision alone is no longer sufficient. With typical process windows, the size of features could be allowed to vary within ±10% of target. Typical precision requirements have been 10% of the allowable process window, or ±1% of target size.
However, as targets get smaller, as with 0.18 µm technology, manufacturers are requiring better CD measurement precision from their tool suppliers. The problem is that the techniques used to calibrate a metrology measurement system, such as a SEM, involve taking sample products from the manufacturing process and measuring them to determine the tool's precision. The downside involves many subtle variations caused by variations in film stack thickness and other factors that make metrology tool calibration problematic. In the case of CD-SEM, the lack of linewidth standards is beginning to make itself felt and is slowly being addressed by both tool manufacturers and users. Bill Banke and Chas Archie, of IBM Microelectronics and IBM Advanced Semiconductor Technology Center, argue that tool evaluation for accuracy requires well-characterized artifacts. Artifact creation not only shares many of the problems involved in producing standards, but also affects properties that vary similarly to the products to be measured in the manufacturing line.
Tool manufacturers are beginning to address some of these problems in ingenious ways. For example, at SEMICON West, Surface/Interface Inc. (Sunnyvale, Calif.) will introduce its Stylus NanoProfilometer CD-metrology tool, which provides deep submicron true profile measurement of lines, trenches and other features. The profiles quantitatively characterize features without physical cross-sectioning, and the system serves as a calibration tool for CD-SEMs, adding needed accuracy to their precision. As its name implies, the system combines elements of traditional scanning probe microscopy and stylus profilometry with force-and angle-controlled sensing technologies.
Yield management
Yield engineering's continued focus on managing vast amounts of data and filtering it into yield improvement activity will accelerate as new fab build plans become a reality. The Greenfield approach will afford a tremendous opportunity for in-line yield improvement and real-time tracing of yield problems to the process tools causing defects.
CD metrology management intensifies as, for instance, microprocessor manufacturers are continually pressured to increase the number of parts binning at 400 MHz and higher. The effect on yield management is an increasing need for higher throughput CD-SEM measurement and a shortening of the defect reduction loop to identify defect sources more rapidly.
Reticle error management is much more difficult in the subquarter micron world than ever before. Greater cooperation among designers, process engineers and the mask supplier is desperately needed to deliver the highest yielding mask sets.
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| Fig 4 Three-dimensional packaging is gaining acceptance, particularly in the form of stacked memories. (Source: Fujitsu Microelectronics) |
From a commercial standpoint, much of the progress in data management is software-based, though better inspection tool-to-tool matching is also becoming more essential. Leading-edge fabs are using holistic yield management, integrating the most crucial data from inspection tools with probe results to keep up with the changing landscape of defect types. This is especially true in CMP processing, now used to form shallow trench isolation structures, tungsten contacts and copper interconnects. Engineers have yet to identify all the defect signatures resulting from this evolving wafer processing technique.
Assembly and packaging
Three major trends are taking shape in assembly and packaging: increased need for collaboration between chip, package and board designers; further development of three-dimensional packaging technologies; and increasingly open automation.
The fusing of chip, package and board making is starting to take shape, as evidenced with increasing use of chip scale packages (CSPs). Rigid-substrate and flexible-interposer types resemble classic packages, but some custom leadframe and all wafer level package types resemble a mere add-on to the die. Some have started to take power planes and clock trees off the die to put them in the package. That is fusion.
The use of integrated passives fuses the package with the circuit board. Multichip modules (MCMs) have been used for some high-performance applications over the years. The term 'multichip package' is gaining use, indicating increased commercial adoption of MCMs in the near future. In the MCM concept, the package performs some interchip connection that the board normally would provide. Multichip packages offer one alternative to system-on-a-chip, SOC.
Three-dimensional packaging has already been commercialized in stacked memory devices, as well as in military and aerospace applications. Most 3-D technologies connect peripherally-leaded dice together. At least one other package puts multiple die on a flex substrate, which is folded to save space. Some engineers are working to directly connect area-array die. Patents for supporting technologies are in place with more coming. Such alternatives to SOC should succeed if economical.
The level of automation in packing operations continues to increase. More people use wafer maps, and the desire to implement full chip traceability with increasing product volumes makes computer integrated manufacturing a necessity. Fully-automated lines increase tool utilization. Plug-and-play type integration work is starting to take place, with most major equipment companies agreeing on an open integration architecture.
Factory automation
Semiconductor manufacturing is no longer technology limited; it is productivity limited. Automation must be in place for consistent and predictable material movement. Also, the data handling requirements in a fab are increasing exponentially to meet yield management and process control needs. Those needs are reaching the point where data handling infrastructure must be in place first, before the tools. Every piece of information from engineering lots is vital for process ramping and control, especially now as the number of engineering lots must decrease.
Advanced process control has been used to some degree in different places,
but only now has the need for improved productivity driven more manufacturers to
give it serious consideration. Run-to-run recipe adjustment improves critical
parameters consistency on the wafer, while extending the time between
maintenance operations on the tool. Multivariate statistical process control
(SPC) sees surprisingly little use on tools, though it promises a great deal of
cost savings from reduced scrap. Feed-forward techniques have the potential to
'save' wafers from becoming scrap, or at least increase the number of devices
binning at higher performance levels.
