Analyzing Probe Yield Sensitivities to IC Design
Laura Peters, Senior Editor -- Semiconductor International, 5/1/1999
Part 4 of Series
Part 4 in this series of articles on Integrated Yield Management by Nick Atchison and Ron Ross of Silicon Systems (Santa Cruz, Calif.) describes an analytical method that rapidly identifies design sensitivities and process sensitivities early in the development cycle of new products. It also provides insight into which electrical parameters affect specific parametric tests. The analysis can be performed after only three lots and at least 60 product wafers have been tested. The complete article, 'A New Method for Analyzing Probe Yield Sensitivities to IC Design', is one of several subsequent papers to 'A Comprehensive Sequential Yield Analysis Methodology,'' summarized in Semiconductor International, January 1999, p. 38. The analysis that follows fits into the 'Refined Yield Analysis' portion of the IYM Triangle, as causes of yield loss can be extracted using this methodology.
The analysis relates parametric test parameters such as output levels, offsets, frequency responses, etc., to device parameters such as transistor betas, threshold voltages, sheet resistances, etc. Using parametric values at site-by-site locations on the wafer (at least 5 sites/wafer), the analysis is much more sensitive than methods using wafer average data.
First, the user generates a wafer probe test pareto for a group of at least 60 wafers from three or more different wafer lots. The pareto shows percentage of dice failing going into each test, making it possible to select the wafer probe parameters with the highest failure rate on which to perform product sensitivity analysis. Next, histogram plots of the distribution of each of the top few tests on the pareto show the spec limits (upper and lower axes of histogram).
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| Fig. 1. This plot indicates design-related yield loss, as the design should have encompassed the entire spec range from 160-240 resistance values. |
As shown in the Figure, the best-fit line extends below the lower spec limit of the probe parameter while still within the electrical test spec window. In this case, there is a yield problem. The probe parameter would start to fail at approximately 200, well above the lower spec limit of 160. This example illustrates a definite design issue.
As explained in the article, if a wafer probe parameter is sensitive to a
given device parameter, it will show a similar sensitivity to all other device
parameters that correlate with the given parameter. Atchison and Ross developed
a method to adjust yield limits to avoid counting the same yield limits more
than once, as explained in the previous paper, 'A Useful Method for Calculating
Parametric Yield Limits.'
