Optimizing RTA Ramp Rate for Ultrashallow Junctions
Aditya Agarwal,
Semiconductor Equipment Operations,
Eaton Corporation, Beverly, Mass.
Anthony T. Fiory and
Hans-Joachim L. Gossman,
Bell Laboratories,
Lucent Technologies, Murray Hill, N.J.
-- Semiconductor International, 5/1/1999
 The risk associated with changing any one parameter can be reduced by varying another parameter instead.  |
In this article, we systematically examine the effect of ramp-up rates on diffusion and shallow junction formation during spike anneals -- fast-ramp-up anneals that spend essentially zero time at-temperature. The achievable reduction in junction depth with increasing ramp-up rate decreases with increasing implant energy, becoming observable at 5 keV for a 2 x 1014 cm-2 boron dose. The observed reduction for 0.5 keV implants results from straightforward decrease in total thermal budget. While in principle a higher ramp-up rate should reduce TED, simulations indicate that the reduction in junction depth begins to saturate beyond moderate ramp-up rates of 50°C to 100°C/sec. In practice, even the fastest ramp-up must eventually be slowed down to stop at, and not overshoot, the target temperature -- resulting in significant rounding of the temperature-time profile. The effect of the rounding is to dilute any beneficial effects of the highest ramp-up rates.
The data show that an integrated process solution for forming ultrashallow p-type junctions will necessarily require a combination of ultralow energy (ULE) implants with a spike anneal and the simultaneous optimization of implantation and annealing parameters. For example, with a suitable understanding of all the parameters involved, anneals at moderate ramp rates (< 100°C) can be used to reproduce junction properties achieved using ramp-up rates of hundreds of degrees per second.
Increasing ramp rate, reducing RTA time
Though junction depth, xj, can be limited by annealing for a sufficiently short time at greatly reduced temperature (e.g., 750°C/10sec), this results in decreased dopant activation and insufficient damage removal leading to a large sheet resistance, Rs, and increased junction leakage, respectively. Thus, it is necessary to anneal at the highest temperature possible while limiting the total thermal budget for dopant diffusion. A spike anneal meets these requirements for minimal thermal budget, by reducing the RTA soak time from the typical 10 seconds to virtually zero seconds. Fast ramps to and from the target temperature can further reduce thermal exposure. However, while the ramp-up rate can be increased to hundreds of degrees per second in today's RTA equipment, the ramp-down rate cannot.
Ion implantation and TED
Dopant diffusion is inevitably modified by the damage to the silicon crystal that occurs during the dopant implantation process. Implantation breaks Si-Si bonds and creates Frenkel-pairs consisting of vacancies and self-interstitials. During the initial stage of annealing, most vacancies and interstitials recombine, leaving behind excess interstitials approximately equal to the implanted ion dose according to the '+1' approximation.2 Excess isolated interstitials quickly coalesce into extended defects such as dopant/interstitial complexes3 and/or planar clusters of Si-interstitials.4 In the latter case, these cluster defects have a lower free energy than isolated interstitials, but greater than that of a perfect crystal: the defects are thus metastable and subsequently dissolve. Released interstitials diffuse to the surface or into the bulk, where they are annihilated or trapped by other point defects such as carbon or oxygen atoms in the silicon. As long as extended defects exist, an interstitial supersaturation is maintained in their vicinity.
Since boron diffusion is driven by Si interstitials, interstitial supersaturation enhances boron diffusion. The enhancement ends soon after the defects dissolve. A consideration of interstitial supersaturation and time to defect dissolution5 allows the increase in junction depth, ?xj, due to dissolution of Si interstitial clusters, to be expressed as: 6
D xj2 ~ Rp e - (-Ef + Eb - Em)/kT
where Rp is the projected ion range; Ef +Em = 4.9 ±0.1 eV is the activation energy for Si self diffusion, consisting of the self-interstitial formation and migration energies, respectively; and EB is the energy barrier for B diffusion, equal to 3.46 eV.7 Activation energy of D xj2, is ' - 1.4 eV when boron diffusion is dominated by interstitial-type defect dissolution.8
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Fig. 1. Sheet resistance increases with ramp-up rate for various combinations of B implantation energy and dose, after 1050°C spike annealing (a). Percent increase in Rs (b) is greater when ramp-up rate is increased from 70 to 155°C/sec, than when increased from 40 to 70°C/sec. |
The negative activation energy of ?xj predicted by Equation 1 means that if TED is allowed to run its course (defects are allowed to dissolve) at 750°C, the increase in junction depth due to TED will be greater than if TED is run out at 1000°C. This is one of the main reasons RTA replaced traditional furnace annealing for junction activation. A conventional furnace's ramp-up rate of <5°C/sec prevents it from reaching the high temperature needed to minimize sheet resistance without incurring a large penalty in junction diffusion.
The negative activation energy of TED also argues for very high ramp rates, since less time spent at the lower temperature minimizes boron TED. Consequently, ever since the first report of a 30 nm junction formed using a high ramp-up rate of 400°C/sec9, RTA manufacturers have been interested in developing high ramp rate RTA capability and in determining the technology node1 at which ramp-rates may become a 'show-stopper.'
Equation 1 also predicts that TED decreases linearly with implant depth, Rp. This fact, recently demonstrated experimentally,10, 11 implies that TED can also be reduced by reducing the implantation energy, making it feasible to manufacture shallower junctions by ULE ion implantation.
Sheet resistance and junction depth
The effect of ramp-up rates on junction parameters such as Rs and xj , and on enhanced diffusion, was investigated using various combinations of boron energy and dose. Silicon wafers were implanted to a high dose of 2x1015 cm-2 at 0.5, 2 or 5 keV, or to a low dose of 2x1014 cm-2 at 0.5 and 5 keV, then annealed in a lamp-based RTA at ramp-up rates of 40°C, 70°C and 155ºC/sec and in a hot-walled furnace at 55°C and 85ºC/sec. The ramp-up rate was calculated as the average rate from 700°C to the target spike anneal temperature of 1050°C minus 10°C (specification of the ramp-up rate to within a few degrees of the target temperature is desirable since the impact on thermal budget is greater in this regime). Standard 3-second soak anneals were also performed using a ramp rate of 155ºC/sec. Ramp-down rate was constant for all anneals at 60-70ºC/sec.
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Fig. 2. SIMS depth profiles following lamp-based 1050°C anneals show increasing junction depth with slower ramp rate and 3-second soak time (a), while depth differences are much less significant at the higher energy of 2 keV (b). |
For all energy and dose combinations, Rs increases with the ramp-up rate, regardless of the furnace type (Fig.1a). Interestingly, the increase in Rs (Fig.1b) is greater when the ramp-up rate is increased from 70 to 155°C/sec, than when increased from 40 to 70ºC/sec. Though the reduction in thermal budget from increasing the ramp-up rate from 70 to 155ºC/sec is smaller, the penalty imposed by the increasing sheet resistance is larger.
A comparison of the junction profiles at different energies shows that the reduction in junction depth achieved by increasing ramp rate from 40 to 70 to 155°C is greater for the shallower 0.5 keV implant (Fig.2a) than for the deeper 2 keV implant (Fig.2b). The same trend is observed for the lower boron dose of 2x1014 cm-2 (Fig.3): while the high ramp-up rate of 155°C leads to a shallower junction for the 0.5 keV implant, the difference in 5 keV profiles is indiscernable.
It is clear that at the lowest energy of 0.5 keV, where TED does not dominate diffusion and xj is controlled by the thermal budget only, a further improvement in junction depth could be achieved by increasing the ramp-down rate. It is, however, inherently difficult to increase the ramp-down rate in today's RTA equipment due to poor radiation coupling during cooling (the heat source does not cool down rapidly).
Figure 4a summarizes the data in Figs.1-3 by considering Rs as a function of xj; the data are grouped by boron energy and dose combination. The trend, pointed out previously in Figs. 2a and 2b, of diminishing advantage from a high ramp-up rate with increasing implant energy is also apparent in Fig.4a where the vertical and lateral spread (Rs and xj, respectively) between data points, corresponding to different ramp-up rates, decreases with increasing implant energy. The impact of higher ramp-up rates decreases with increasing implant energy.
Spike vs. soak anneals
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Fig. 3. Higher ramp-up rate produces shallower junctions at 0.5 keV implant energy, while its effect at 5 keV is negligible. |
Alternative shallow- junction process solutions
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Fig. 4. Summary of sheet resistivity and junction depths using spike anneal data (a); comparison of hot-walled RTA of 0.5 keV/2x1015 cm-2 at 85 and 50°C/sec, with lamp-based RTA of 1 keV/1x1015 cm-2 (preceded by 1x1015 cm-2, 5 keV Ge pre-amorphization) at ramp-up rates of 400°C, 200°C and 25°C/sec (b). |
Figure 4b compares data from a previous process optimization experiment12 that included the highest ramp-up rate reported in the literature so far for lamp-based RTA, with some of the data from this study obtained using moderate ramp rates in a hot-walled RTA. In the previous experiment12, a 1x1015 cm-2, 5 keV Ge pre-amorphization step was followed by a 1x1015cm-2, 1 keV B implant and a spike anneal at 1100°C with ramp-up rates as high as 400ºC/sec. The extremely shallow 40 nm junctions yielded by that process can be reproduced by a 2x1015 cm-2, 0.5 keV B implant with 85ºC/sec ramp to 1050ºC in a hot-walled RTA. It is obvious that some of the advantages of very aggressive ramp-up rates can be engineered by varying other RTA and implant parameters. There exists a tradeoff between many of the implantation and annealing parameters, which necessarily implies that the risk associated with changing any one parameter can be reduced by varying another parameter instead. For example, in the case above, selecting the moderate 85°C/sec ramp rate is preferable for thermal uniformity considerations.
Implications for integrated process solution
At this time, it appears that extremely shallow p-type junctions needed for
0.13 and 0.10 µm device generations can be achieved by combining 0.5 keV ULE B
implants with spike anneals. While high ramp rates are expected to significantly
reduce xj and simultaneously achieve low Rs, in practice,
only the ramp-up rate can be greatly increased. The advantage of high
ramp-up rates is limited by the slower ramp-down rate for conditions where
diffusion is controlled by thermal budget only, not by implantation damage
(e.g., for 0.5 keV B implants). It is also clear that a high ramp-up rate is
advantageous only when it is part of a spike anneal. It has been shown that the
effects of the high ramp-up rates can, in some instances, be duplicated by
varying other RTA or implantation parameters. The final choice of ramp-up rate
will be, therefore, dictated by the risks (uniformity and repeatability) of the
implantation and annealing parameters together. 
Acknowledgments
We thank John Jackson of Eaton Implant Systems Division for ULE B implants and Peter Frisella of Eaton Thermal Processing Division for hot-walled RTA anneals.
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