Thermal Processing Options Focus and Specialize
Alexander E. Braun, Associate Editor -- Semiconductor International, 5/1/1999
 The thermal budget control road is a rocky one, and its ups and downs do not only pertain to temperature.  |
'We've focused on developing the technologies required to manufacture the most advanced transistor structures,' said Dr. Israel Beinglass, managing director and CTO of Applied's Thermal Processes and Implant group. 'Today, if you look at implant and shallow junctions, the industry standard for 0.18 µm is between 2 and 1 keV boron. In successive generations, boron energy requirements will be below 1 keV. Also, there is a trend to accelerated RTP ramp rates; 50°C/sec was sufficient and now 150°C/sec and higher are being explored. We're addressing this with an ultrashallow junction module that combines a low energy ion implanter with our RTP system, which can ramp up to 250°C/sec.'
Beinglass does not believe ramp rates above 150°C/sec are advantageous. 'One can do 200 or 250°C/sec, and although it may be necessary to go to a faster ramp for 0.10 µm, it's an open issue because of lower implant energy requirements for this technology node. For 0.18 µm, 150°C/sec appears optimal.'
According to Larry Bourget, director of Applications Engineering at Eaton Thermal Processing Systems (Peabody, Mass.), the fast ramp-up issue is wide open. 'RTP companies make claims, but it still remains to be seen what 'fast ramp-up' really means.'
Presently, it is unclear if a ramp-up rate above 150°C/sec is needed to meet 0.10 µm shallow junction requirements. Diminishing returns set in with ramp rates above 150°C/sec, when cool down rates are limited to 60°C/sec or less as in typical current RTP systems. For reduced thermal cycling during spike anneals, ramp down rates of 100°C/sec are more important than ramp rates above 150°C/sec (Fig. 2).
'Beyond 0.10 µm, plasma immersion ion implant (PIII), or plasma doping are being considered,' said Applied's Beinglass. 'Implant tool manufacturers are increasing the current and progressively getting better current at a low energy, but we don't know what the limitations of current technology are. Current thinking is that the transition might occur at 0.10 or even 0.07 µm,' Beinglass said.
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Fig. 1. Thermal processing technology is facing one of the most demanding periods in its history, as smaller and denser architectures on increasingly larger wafers force lower thermal budgets and higher throughputs are required. (Source: Mattson) |
While it is true that RTP had relatively small marketshare, when Applied Materials entered it RTP ceased being considered a laboratory curiosity. Mattson recognizes this. 'Applied brought maturity to the market. Before, competitors tried to beat each other on price, not technology. Applied competes on technology and decided to solve the technical problems and not worry about price. That being said, however,' he pointed out, 'Traditional lamp-based RTP still has many problems in production and is significantly more expensive than furnace processing.'
Mattson noted RTP has gone into limited segments where there is no choice except RTP. 'There are only two areas that I know of - implant anneal, where you really need a very short process time. The other is when the wafer's environment cannot be controlled due to the metal surface's oxidation and a well-purged environment is needed, something hard to do with big batch furnaces.'
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Fig. 2. This RTP fast ramp spike anneal exhibits excellent multipoint temperature control during fast ramp-up and cool-down. (Source: Applied Materials) |
Nitin Shah, director of Marketing and Technical Sales at AG Associates (San Jose, Calif.), believes thermal processing and RTP requirements are driven by shallow junction formation. 'When geometries shrink, everything else follows, junction depths, everything, which is why thermal budgets must go down.'
STEAG RTP Systems (Austin, Texas) expects RTP to be used increasingly for very shallow junctions. 'This is going to be a different way of doing junction engineering especially putting the implant together with the RTP step,' said Jeffrey Gelpey, vice president for technology. From work done with Varian on ultra-shallow junctions, STEAG has determined that work must proceed concurrently on both parts of the process in order to take advantage of it.
The Gate Dielectric
Applied believes the trend from batch- to single-wafer tools will continue, fueled by technical advantages and the capability to reduce cycle times and width. 'Fabs may have a furnace operation at the front end, but the back end has gone to single-wafer,' said Beinglass. Although fabs built during the last two years still have furnaces, these are fewer. 'We used to anneal in the furnace. Now, practically nobody does it, it is all RTP,' observed Beinglass. 'Other steps haven't changed; the oxidation gate, for example. Soon we'll refer to it as a 'gate dielectric' because there won't be gate oxides anymore, but gate dielectrics that will be oxide nitride, possibly high-k materials or something different.'
Oxidation still takes place in furnaces, and there is LPCVD, like poly and nitride. 'For gate, SiO2 is reaching its limit at 30 Å for the 0.18 µm technology node. For 0.13 µm, the equivalent oxide thickmess will be 15 to 20 Å, and at 0.10 µm about 10 to 14 Å.'
Gate oxide in the 20 Å region presents twin problems. First, boron penetration from the poly. Second, tunneling through the thin gate oxide. Nitridization, or some nitrogen within the oxide, is a solution. 'Initially oxide will be used with some nitridization using a nitric oxide or nitrous oxide process. Later on, a very thin layer of SiO2 followed by thin LPCVD nitride may be used as the gate dielectric,' pointed out Beinglass.
A good and well-characterized interface is still needed, however, and with 20 Å, there is little margin. While at 0.13 µm, there will be some oxide and nitride; the big question is what happens at 0.10 µm and beyond. High-k materials like Ta2O5, TiO2, or similar materials might be good gate dielectric candidates. Materials issues will dominate the industry for the next five or ten years.
Nitride Applications
Nitride spacers used to be processed around 800°C in a furnace, but 0.15 µm and 0.13 µm thermal budget constraints do not allow it and furnace processing takes hours. A one- or two-minute single-wafer RTCVD process significantly reduces the thermal budget. 'We believe,' said Beinglass, 'that at 0.15 or 0.13 µm single-wafer equipment will be used for various LPCVD nitride applications.'
'Ten years ago, only one layer of nitride was used and maybe three layers of poly,' recalled Beinglass. 'Things are changing. In standard logic there is only one poly as the gate. Flash and EPROM have two, DRAM more. Nitride is up to three or four layers - we're using it in the isolation, in STI, and the spacer. It's even being used as an etch stop and hard mask. Single-wafer nitride will be in demand for future generations.' On the matter of integrated gates, Beinglass added, 'A single system with RTO/RTP, nitiride and poly chambers can provide a complete gate and gate electron solution, without exposing the wafer to the atmosphere.'
To RTP or Not to RTP
A relative newcomer to thermal processing, Mattson confronts thermal budget problems differently. The company's entry is a uniquely designed furnace. 'We didn't try to do a fast lamp-based system,' explained Brad Mattson. 'We built a small, very compact furnace that's vacuum isolated and vacuum loadlocked and far more efficient than a standard furnace. It raises wafers to temperature quickly, they come out and cool quickly.' The system achieves extremely fast ramp-up and ramp-down profiles - and therefore, short time at temperature - similar to lamp-based RTP. 'Because it's small, vacuum-isolated and loadlocked, purging and control of the gaseous environment around the wafers for certain sensitive metals is very efficient.'
The design appears to combine the best of the standard furnace and RTP. 'We've the benefits of high reliability and low cost, with excellent uniformity and repeatability. The system looks, acts, and feels like a furnace with RTP's speed and control. Throughput is typically 50% to 100% higher than lamp-based RTP systems,' said Mattson.
Mattson views repeatability as a major processing challenge. 'With lamp-based RTP systems, repeatability over time remains in question. Lamps degrade, the quartz changes and gets coated. There are many control parameters that, long-term, make it difficult to match the repeatability of furnaces.'
Leaving the Lab Behind
Thermal budgets can be cut in two ways - by reducing temperature or processing time. 'There is a limit beyond which temperature cannot be reduced, because silicon defects must be annealed and dopants activated,' explained AG's Shah. 'The other option is reducing time, and processes are dropping to almost zero time during the high-temperature steady state step. They're becoming spike processes, which means the heat ramps up and when it hits the desired temperature, cooling starts immediately.'
RTP has successfully addressed the thermal temperature regime from 400°C to 1,200°C, and times from zero seconds to up to about 2.5 minutes. 'Furnaces address temperatures from 400°C to 1,100°C, but time ranges from 10 minutes upward,' Shah said. He added that the period between 2.5 to 10 minutes and temperatures less than 400°C is where new applications are emerging. 'Some are copper anneal, others low-k dielectrics - low-temperature medium-time applications.'
At the high end of the temperature application, there is a move to integrated processing. Standalone RTP is expected to lose its hold there. When considering gate or capacitor oxides, an integrated precleaning capability is required. So the RTP system precleans and then grows the oxide. RTP will evolve into an integrated system where multiple processes take place on the same platform, integrating high-k dielectric deposition plus anneal.
Shah agrees with those who believe conventional RTP has reached its full potential. 'If RTP remains the way it is, it'll serve a limited purpose.' He is quick to add, however, that changes are taking place and there are areas not being addressed by furnaces where RTP will take off. 'When low-temperature processes are considered, one must look at two- not one-wafer processing for productivity. RTP has always addressed high technical performance needs successfully, now it has left the R&D lab and must improve productivity, because it's entering a production, not research, environment. Fortunately, all that's required is extra design engineering.'
When Is Fast, Fast?
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Fig. 3. RTP systems, like this Reliance 850, must be flexible, providing process capabilities that include ultra shallow junction formation, salicides, oxide growth and annealing. (Source: Eaton) |
'Throughput is still the name of the game,' stated Eaton's Bourget. Fabs that processed at 30°C to 50°C/sec are now at 75°C to 100°C/sec. 'Do you need to go above 100 or 200°C? That gets into the spike anneal applications,' pointed out Bourget. 'On a standard anneal where you soak for 10 seconds, it serves no purpose to get up there at 100°C/sec. But, if you're doing a spike anneal at zero hold time, then there's junction depth benefit by going to higher ramp rates (Fig. 3).
Bourget believes fast ramp-up is insufficient. 'You've to worry about cooling down, too.' The cool-down rate sets limits on the thermal budget at the spike's top. As Bourget put it, 'At 0.10 µm, the industry may reach a limit in its ability to hit junction depth and still control sheet resistance and overshoot and get good uniformity.'
Bourget continued, 'Customers claim they want specific ramp rates. When we ask how they measure ramp rate, we rarely get a straight answer. If you plot out ramp rate as a function of temperature, as you approach processing temperature you must have zero ramp rate at that temperature, otherwise you overshoot. So the ramp rate versus temperature curve resembles a buffalo's hump - it goes up then drops down at process temperature. When you ask what the ramp rate is, they give you a peak ramp rate or an average between two temperatures.'
There is uncertainty as to what ramp rate is needed, because cool-down rates are becoming a concern. 'What you care about is the time spent close to processing temperature,' said Bourget. 'If on a standard anneal you're looking at a ramp-up rate, you might take 700°C to 5°C below process temperature and look at that average. Obviously, if you get within 5°C of process temperature you better close that loop fast and get back down. For a 1050°C anneal, you'd measure from 1000°C to 1050°C and then back down to 1000°C. The time above 1000°C must be under three seconds for a spike anneal or you sacrifice junction depth.'
Wafer Size and Thermal Processing
Doug Meyer, an executive scientist at ASM International (Phoenix, Ariz.), views wafer size as the challenge posed to thermal processing options. 'The question is,' he said, 'how willing are we to put larger-diameter wafers in furnaces? Presently, nobody's really pushing 300 mm, so everyone lackadaisically seems willing to get by with what they have. But these wafers' thermal budget limitations will have to be considered.'
Although no one questions furnace technology quality, results depend on the process carried out. 'Everyone still builds gate oxides, gate dielectrics, and gate electrodes in a furnace,' said Meyer. 'But if SiGe gate electrodes take off, everything will go to single-wafer - would it necessarily go in that direction for the gate dielectric? Maybe not, because you still have not sunk your source/drains at that depth point, which is the reason for the self-aligned structure.' If Meyer's assessment is correct and SiGe gate electrodes become a mainstay, single-wafer processing will become mainstream. 'Ultimately, single-wafer processing might backfill from 300 mm into 200 mm and even 150 mm.'
CMOS base epitaxy applications will probably remain in the high temperature range, because there is not much on the wafer with thermal limitations, and no way to get desirable throughput at low temperature for films used in CMOS applications. Epi for high breakdown voltage power devices will probably not go to single-wafer processing since a single-wafer machine's throughput is inadequate for 50 µm or 100 µm epi layers, which require substantial deposition and chamber etching times.
Meyer believes interconnect challenges should be interesting because copper probably puts few constraints on the thermal budget. 'The issue in metal interconnect structures was that there would be blanket aluminum deposition, then etch holes, and fill them with dielectric. The difficulty was getting a good quality dielectric in and minimizing void formation, while keeping the temperature under 400°C so to keep from melting the aluminum.' Copper's high melting point eliminates most of these problems. However, the process has been reversed. Blanket dielectrics are deposited, holes etched and then filled with copper to serve a double purpose (dual damascene): the via and the interconnect. Now, the quandary is what happens with low-k materials. Copper provides low-resistance interconnects, but low-k material is necessary to minimize coupling between adjacent interconnect lines.
Meyer believes wafer passivation will be the final thermal process, although it is plasma enhanced. Historically, a phosphorus-doped glass was used as a sodium blocker and silicon nitride was placed on top of it. Now, new precursors will be needed to keep temperatures low enough to avoid low-k dielectric shrinkage. Low-k film stability and how much temperature must be applied to passivate a wafer could become a major issue, because plasma nitrides are in the 300°C range. Low-k is not the sole consideration - extremely temperature-sensitive polymers are entering the picture.
Temperature Control and Uniformity
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Fig. 4. Multipoint measurement and multiple-input control systems are important, but so is inherent equipment uniformity both at steady-state and during ramps. (Source: STEAG RTP Systems) |
STEAG's Gelpey believes RTP has made great strides in temperature uniformity and measurement. 'Realistically, state-of-the-art for uniformity is about ±2.0°C to 2.5°C across a 200 or 300 mm wafer at steady state - all points all wafers. That's a combination of the uniformity and the capability to measure temperature with different backsides.'
This seems sufficient for what most need at 0.18 µm, and close to meeting 0.13 µm needs. 'The barrier is 0.10 µm,' observed Gelpey. 'There is where additional improvements in both temperature control and uniformity are needed.'
There is a factor Gelpey refers to as 'dynamic temperature uniformity,' which may cause problems. 'Most look at uniformity when the wafer sits at constant high temperature. However, what happens during ramp-up and ramp-down can be more important, especially with shallow junction processes. These are moving to no-time at high temperature - spike anneals.' (Fig. 4)
These dynamic effects tend to be difficult to control and measure, because steady-state uniformities are measured by process results, like implant uniformity or oxide growth uniformity. That does not indicate what happens during the ramps. 'This is important,' said Gelpey. 'If you don't maintain good uniformity during the ramps, you revive problems solved years ago with RTP such as slip and pattern distortion, where things move around and get frozen where they're not supposed to be.'
The 300 mm Perspective
Bob Herring, director of process technology for SVG Thermco (San Jose, Calif.), sees four key RTP development areas: the trend to larger wafers, device shrink and its influence on film types and thicknesses, thermal budgets, and equipment issues.
'We're working with two 300 mm pilot lines,' said Herring. 'So far, we've been able to translate and hold all film properties and uniformities on all the thermal processes for 64 MB DRAMs in the transition to 300 mm. Now we're doing scaling and development on 256 MB devices.' Herring expects that several processes will remain in batch mode, even at 300 mm, because of productivity and cost considerations.
As shrinks progress, films will get thinner and the use of sequential processes will increase; that is, film stacks developed to be done in the same reactor, the same chamber. Some are oxide, poly, or poly emitters in CMOS devices, also oxide nitride sandwiches and oxide nitride oxide structures, as well as others.
'We've developed processes that control oxides down to 10 Å, capped in place with the poly layer or the poly emitters,' said Herring. 'It had been assumed it wouldn't be possible to do these thin oxides and transfer them to another system for the next layer, without a cluster tool. The solution is to do them in one chamber. So we do the oxides at reduced pressure, which is an efficient way to control growth rate. There are very dilute oxide or very dilute steam processes to slow down oxidation kinetics, but reducing pressure controls the oxygen's partial pressure with excellent uniformity over the load.'
SVG has developed a system capable of ramp-ups approaching 100°C/min. 'Fabs run it in enhanced mode with a full wafer load - it takes 150 wafers and ramps them up or down at 25°C/min.' According to Herring, fast ramp batch systems will eventually be capable of doing 50-wafer loads at a high ramp rate: 100°C/min up, 50°C/min down.
'RTP systems deal in degrees per second, but if you can reduce that temperature over about 50°C, you slow down diffusion rates,' pointed out Herring. 'What really controls thermal budgets is the approach to temperature and getting back down below some point that slows lateral diffusion.'
Herring considers contamination a major challenge for 0.10 µm. 'We've learned how to control classic particles. As we go below 0.20 µm, we see film defects that relate to molecular-level issues such as organic contamination, whether from the fab environment or the clean or any of many sources. This is not limited to furnace processes; it has already been seen in lithography processes, some of which use organic absorption filters. It probably has been there all along, but was not obvious until we got down to the finer geometries.'
Equipment design for furnaces and certainly RTP systems
is in a state of flux. As new materials and increasingly stringent processing
requirements come along, the industry will respond as it always has, with
innovation and good engineering.
