IMEC Readies 0.13 mm & 0.10 mm CMOS Processing

-- Semiconductor International, 11/1/1999

The Inter-University Microelectronics Centre, (IMEC, Leuven, Belgium) has set up industrial affiliation programs in which mixed research teams are addressing several challenges that must be overcome for introduction of 0.13 µm technology. These include the use of 193 nm optical lithography, copper metallization and low-k dielectrics as inter-metal materials. Fabrication of devices with features half the size of the laser wavelength will require better phase shift masks and optical proximity correction.

The key IMEC industrial affiliation program (IIAP) on 193 nm lithography now has more than 25 partners, including material and equipment suppliers and semiconductor manufacturers from all over the world. Luc Van den Hove, vice-president of silicon process technology at IMEC, said: 'In this consortium, the cost of the development activity is reduced by a cost-sharing mechanism, a benefit typical for the IIAP co-operation scheme.' This program involves resist evaluations and detailed stepper assessment.

As layout and technology rules are downscaled, the importance of interconnects on overall circuit delay increases due to the reduced metal spacing increasing stray capacitance. Thinner and narrower lines have to be used. Many companies are participating in the IMEC IIAP back-end program to jointly develop advanced multi-level metallization. The work includes copper dual-damascene for 0.15 µm and smaller dimensions, dielectrics with k values of less than 2.5 and chemical mechanical polishing. The IMEC pilot line has been extended and equipped with a copper area where development has started on 0.13 µm and 0.18 µm copper technologies.

The scaling down of CMOS processes to less than 0.18 µm may result in reliability problems in the gate stack, such as increased sensitivity to boron diffusion from the gate via the thin gate dielectric layer into the channel. Shallow trench isolation will replace LOCOS-based isolation technologies for 0.13 µm and below, as it can be more easily scaled down without a significant cost increase.

Scaling down the dielectric layer towards a few nm will change the physical and statistical aspects of intrinsic breakdown. Ludo Deferm, associate vice president for silicon technology and device integration at IMEC, said: 'New dielectric layers with a high dielectric constant, such as Ta₂O₅ and/or metal gates, are being explored, including their compatibility with standard CMOS processing. By pooling resources, the consortium will reduce risk and gain early process knowledge at lower cost than through individually funded R&D work.'

The continually accelerating Semiconductor Industry Association roadmap now calls for a 0.1 µm process by 2003, two years earlier than forecast only last year. IMEC and ASML (Veldhoven, Netherlands) already are considering initiating a 157 nm wavelength process that should deliver production tools by 2003. ASML and Carl Zeiss have carried out initial design studies on the feasibility of a high numerical aperture lens that will enable greater resolution and process latitude at 157 nm than is available from 193 nm technology.