Wafer-Level CSP Incubator Formed

John Baliga, Associate Editor -- Semiconductor International, 11/1/1999

Thomas Di Stefano, former CTO of Tessera (San Jose, Calif.), has formed Decision Track, a technology incubator aimed at unlocking opportunities in wafer-level packaging. In its initial role as a technology development company, the firm plans to help suppliers to the chip-scale packaging (CSP) and interconnect infrastructure mine new business in device design, manufacturing, logistics and materials in support of wafer-level packaging. The statements Di Stefano made in conjunction with announcement of the new company indicate there is more to be gained from wafer-level packaging than reduced material costs and more efficient processing.

According to Di Stefano, equipment and materials are not the limiting factor in developing an infrastructure for CSPs; information is. 'Now the gating items are information and hard data about the demands, equipment, processes, patents and markets for chip-scale electronics,' said Di Stefano. 'One commodity which has been offered in abundance is misinformation about the requirements for meeting the challenges of wafer-level packaging,' he added. 'We intend to present CSP market participants with the means and the expert knowledge to avoid the missteps which have plagued so many companies in the past.'

The addition of interconnect layers brings opportunities for wafer-level packaging to aid IC performance Di Stefano specifically mentioned two: high-performance power and ground distribution on the IC itself, and routing critical nets in the package interconnect layers. These concepts are behind the development of Tessera's WAVE (wide area vertical expansion) technology, also known as 'tiles.'¹

Higher-quality power and ground distribution are needed at the wafer level, especially with signal levels at the level of one volt. There is a limit to the amount of metal that can be placed in the wafer-level interconnects due to thermal expansion mismatch. Placing them in a package layer that is attached to the wafer with a stress decoupling layer allows them to be larger, and therefore more effective. Clock tree structures also can be improved if moved off the wafer itself and onto the stress decoupled package layer.

With wafer-level packaging, it is easy to see the need to co-design the chip and its package. In addition to optimizing factors like material use and thermal performance, changes such as moving power planes and clock trees off the silicon can lead to an even more effective chip-package combination. Wafer-level packaging opens up that extra design space, and it needs to be explored.   

References

1. J. Baliga 'Will Copper Interconnects Move Out on the Tiles?' Semiconductor International, April 1998, p. 52

  Will There be an I/O Catastrophe in 2010?

For as long as semiconductor design rules have continued to get smaller, there has been fear that circuit densities would increase past the capability of routing I/O connections away from the chip. A paper given recently by Mark Kuzawinski of IBM addresses the nature of this problem for projected I/O needs in 2010.

For a 15 mm die, the wirebond limit is about 1500 I/O for a 40 µm wire pitch. Some wirebonding experts believe 40 µm to be a practical limit because the thin wire required at that pitch can barely stand up to the encapsulation process. For area array I/O (flip-chip), the limit seems to be 10,000, for a 150 µm ball pitch. Using flip-chip interconnection, the I/O needs of 2010 can be met for a 15 mm die.

Routing I/Os off the die is not where the catastrophe would take place. It would take place where the package meets the board. With a 1.0 mm pitch, a BGA with 10,000 I/Os would be 100 mm. If a 0.5 mm pitch is used, the package becomes 50 mm. Assuming the most aggressive interconnection technologies, 150 µm and 0.5 mm ball pitches, the packaging efficiency is less than 10%. In other words, the package is more than 10 times as big as the die.

One answer to this catastrophe is to design systems so inter-chip I/O densities are minimized and high bandwidth communication is all done intra-chip. This is being done, but is it enough? Packaging technology may have to make a discontinuous leap to avoid an I/O catastrophe in the next 10 to 20 years.   

Assembly and Packaging News

• ASM Pacific Technology Ltd. (ASMPT, Hong Kong), gained new customers for its AB339 wire bonder. 'The largest chip assembler in the world' committed to more than 100 bonders, and 'Malaysia's largest independent assembler' purchased more than 50. http://www.asm.com/
• Camstar Systems Inc. (Campbell, Calif.) announced that its MESA manufacturing execution system (MES) has been deployed by Unitive Electronics Inc. (Durham, N.C.) as part of a manufacturing expansion and upgrade program that will increase plant production to an eventual capacity of more than 100,000 wafers per year. http://www.camstar.com/
• Tessera Inc. (San Jose, Calif.) has licensed its CSP technology to Toshiba (Japan) and ChipMOS (Taiwan). Toshiba will use a wirebonded variation of the standard mBGA technology. http://www.tessera.com/
• Amkor Technology (Chandler, Ariz.) and Sharp Corp. (Tokyo) announced an agreement to share stacked-die IC chip-scale packaging (CSP) assembly technologies. Amkor is licensed to use Sharp's tape-based stacked-chip package assembly techniques to build stacked ICs for Sharp and other chip manufacturers, and Sharp is licensed to use Amkor's laminate-based ChipArray technology to package any of its products. Amkor and Sharp already assemble stacked-chip CSP ICs using their own technologies, and this agreement calls for co-development efforts. http://www.amkor.com/
• Ultratech Stepper Inc. (San Jose, Calif.) announced the first order for its Saturn Spectrum 3 wafer stepper, from long-time customer Casio Computer Co., Ltd. The new tool was developed in collaboration with Casio specifically for this application. http://www.ultratech.com/
• CR Technology relocated from Laguna Niguel, Calif., to a 20,000-square-foot facility in Aliso Viejo, Calif., to meet an increase in sales volume in the past year. http://www.crtechnology.com/
• Micro Component Technology Inc. (MCT, St. Paul, Minn.) and Aseco Corp. (Marlborough, Mass.) have signed a definitive merger agreement. Roger E. Gower, President and CEO of MCT, said the two test handler companies had surprisingly little overlap, and added that the combined company would be the second largest U.S. test handling system maker. http://www.mct.com/ http://www.aseco.com/
• Dense-Pac Microsystems Inc. (Garden Grove, Calif.) has licensed its three-dimensional packaging technology to Seagate Technology Inc. (Scotts Valley, Calif.). Dense-Pac will receive specific royalties over a two-year period. http://www.dense-pac.com/, http://www.seagate.com/