Intel Previews 100 nm Transistor

Peter Singer, Editor-in-Chief -- Semiconductor International, 11/1/1999

At next month's International Electron Devices Meeting (IEDM), to be held Dec. 5-8 at the Washington, D.C., Hilton, Intel is scheduled to reveal some of the details of a new 'very high-performance, low-power' transistor. With a gate length of only 100 nm, the transistor enabled blazing fast speeds over 1 GHz in a 16 Mb SRAM learning vehicle.

In an abstract provided by conference organizers, Intel reports that the new transistor structure showed a 10% improvement in drive current over the previous-generation NMOS and PMOS transistors, with no change in gate-oxide thickness. NMOS and PMOS devices demonstrated drive current of 1.03 mA/µm and 0.46 mA/µm, respectively, at 1.5V and 3 nA/µm I_OFF. 'These are the best drive currents reported to date at fixed I_OFF,'' according to the Hillsboro-based researchers.

This performance was achieved through several innovations in transistor design, the four primary ones being: implant and anneal optimization; 2 nm physical gate oxide thickness; insertion of a 'notched-poly' process; and a switch from titanium silicide to cobalt silicide.

This 100 nm gate length CMOS transistor features a notch at the bottom of the polysilicon gate, which reduces total gate capacitance.

Intel describes the engineering of the well/halo part of the transistor as 'extremely aggressive.' Arsenic drain extension implants were below 5 keV. Retrograded indium and arsenic wells were used for the NMOS and PMOS devices, respectively. Angled halo implants, performed after gate formation, also were employed.

Intel also developed a gate oxide process that produced a gate oxide thickness of 2 nm, while still meeting various performance, reliability and manufacturability criteria. Interestingly, this is less than the 2.2 nm recently suggested as the 'limit' for gate oxides (See related story below).

A unique transistor feature, clearly seen in the accompanying SEM photo, is a notch at the bottom of the poly gate. This feature, according to Intel, enables a reduction in the total gate capacitance by reducing the gate length dimension at the polysilicon/gate-oxide interface.

By making the move from titanium silicide to cobalt silicide, Intel was able to keep the nominal sheet resistance to below 4 h/sq while maintaining a worst-case sheet resistance of 5 h/sq for polysilicon linewidths down to 100 nm.   

Gate Oxide Uniformity Key to High Reliability

Researchers at Bell Labs (Murray Hill, N.J.) have demonstrated that device reliability can be improved 'significantly' if gate oxide thickness can be made more uniform. Their work, to be presented at the IEDM Conference next month, indicates 1.6 nm gate oxides could be used in transistors operating at 1.2V and 65°C. This TEM shows the 1.6 nm (16 Å) oxide layer fabricated at Bell Labs. The dots in the upper and lower layers are individual silicon atoms. Other researchers have predicted the limit to which gate oxide thickness could be shrunk was 2.2 nm, based on statistics and the temperature dependence of oxide breakdown. The Lucent researchers, however, describe these predictions as 'overly pessimistic' and claim they were based on data from slightly non-uniform oxides. They say improving thickness uniformity leads to a 'significantly better' value for soft breakdown. The oxides they produced had a thickness range of 1.53 nm to 1.61 nm, with a standard deviation of 0.025 nm (Figure). Soft breakdown is typically considered the critical failure point for the gate oxide, but the Lucent researchers have demonstrated that even this is not necessarily true. Many of the transistors they studied continued to operate successfully after soft breakdown. (In soft breakdown a little current leaks through the gate oxide, and hence the device, when it should be off. A 'hard' failure is when there is a definite short circuit.) This should be taken into account, they say, in future studies on oxide reliability.