3-D SOI Using Epitaxial Lateral Overgrowth

Ruth DeJule, Associate Editor -- Semiconductor International, 11/1/1999

Silicon-on-insulator (SOI) wafers are capable of producing low-power, low-voltage devices, essential for scaling gates to below 100 nm. But to achieve gigahertz speed and 10¹² transistors per die, 3-dimensional integration may be necessary to decrease interconnect lengths that impede speed. One approach is 3-D SOI technology -- fabrication of devices in alternating layers of silicon separated by an insulator. For example, PMOS could be on one SOI level and NMOS on a second level with several layers of metal interconnections. The result is a reduction in interconnect lengths from microns to less than tenths of microns, thus decreasing resistance and capacitance, increasing speed, and reducing the circuit footprint.

In an effort to develop 3-D SOI stacks, various studies are underway, including those at Stanford University using solid phase recrystallization and Purdue University using epitaxial lateral overgrowth (ELO). Researchers at Purdue, headed by Dr. Gerold Neudeck, create device size SOI islands as small as 150 nm x 150 nm and as large as 20 µm wide by 3000 µm long using ELO (see Figure). Size limitations lie in lithography and the ability to etch the SiO₂.

Using conventional equipment and silicon processes, layers of SOI are created by forming oxide wells, thermally grown to ~300 nm thick, followed by a lithography step to define the islands. The oxide is etched by RIE. Using low-pressure CVD, silicon epitaxial layers are grown selectively (selective epitaxial growth, SEG), seeded through oxide windows that pick up the atomic template from the substrate or from an SOI island on a preceding layer. At the top edge of the window, growth continues laterally fil ling adjacent recessed wells, to a maximum distance of 20-50 µm, at growth rates of 0.11 µm/min. The location of the SEG windows (as narrow as 200 nm) is defined lithographically. According to Neudeck, initial results indicate high-quality SOI with defect densities lower than those found in current bonded and SIMOX layers.

Fig 1 Forming SOI-2, a second layer of SOI islands: (a) a PECVD insulator is deposited, and wells and a second seed window are etched; (b) SEG and ELO are grown to fill the insulator tubs; and (c) CMP removes excess ELO material.1

To determine the potential effectiveness of ELO, researchers simulated a vertically stacked 4-bit multiplier and compared it to comparable 2-D chips using standard CMOS processing and 0.18 µm design rules. Results were encouraging: The 3-D, 4-bit multiplier had half the interconnect length, slightly less than half the normalized power per device and nearly 75% smaller footprint of comparable 2-D CMOS circuits, according to Neudeck.

In terms of cost, an internal study suggested one ELO layer could be 20% to 30% below the price of current SIMOX wafers with shallow trench isolation or LOCOS, Neudeck said. He asserts that while two lithography steps are needed to form the islands in each layer, no isolation technologies are required, thus eliminating possibly 10 or more process steps. What needs to be done to make this a viable technology? Though the technology is new, Neudeck thinks it's just a matter of fine-tuning -- determining, for example, how to partition the islands to optimize circuit design, and whether it is better to use one metal layer or two. While manufacturing viability is unknown, ELO's flexibility makes it worthy of further investigation.   

References

1. G.W. Neudeck, '3-D Silicon-on-Insulator (SOI) Technologies Using Epitaxial Lateral Overgrowth (ELO),' Electrochemical Society Proceedings, vol. 99-3, 1999, p.25.