New Materials Enhance Memory Performance

		At a Glance
	Memory cell capacitance has been enhanced in several ways as feature sizes have decreased: hemispherical polysilicon and deep trenches for area enlargement, and silicon nitride to increase the dielectric constant. Upcoming generations will require dielectric materials with higher k values, and novel barrier and electrode materials will have to be developed with them. In addition, ferroelectric materials provide a way to store a polarization, and magnetic memory technologies promise a non-volatile memory with fast access times.

As the industry follows the path toward higher-density memory devices, new materials will have to be incorporated. The following techniques are required to maintain memory capacitance as the area per cell shrinks: dielectric thickness reduction, area enhancement and increased dielectric constant. For many films, with or without pinholes, leakage current generally increases greatly as the thickness approaches 5 nm, so there is a practical limit to thickness reduction.

Area enhancement techniques include vertical structures such as fin stacks and crowns¹, capacitor-over-bit-line type architectures and trench capacitors. The first two add complexity to processing and are approaching their practical limits. Trench capacitors can be made deeper, though there is a practical limit to the aspect ratio that can be obtained using reactive ion etching.

Increasing the dielectric constant, k, provides a few benefits. A thicker dielectric can be used. This makes it easier to use the technology while refining the process for making thinner layers. Overly complex capacitor structures are avoided. One proposed roadmap for developing dielectric material systems is given in Fig. 1.

In addition to allowing a higher memory density, ferroelectric memories are non-volatile. They store a polarization rather than a charge, so they use little power; and they have faster access times than current flash technology can offer. Beyond the ferroelectric memory tech nologies are the magnetic memory technologies. They hold the same promise for non-volatility as ferroelectric memories, and their access times are even faster, on the order of 5 nsec. They use the same material sets as read-write heads and hard disks, but the technology must be adapted to wafer processing, which is the main hurdle.

Extending oxide, ONO and NO

Silicon oxide is an established dielectric material for use in memory capacitors. Placing a layer of silicon nitride between two oxide layers increases the effective k value for the dielectric material, since the k value for Si₃N₄ is about 7. Sometimes the nitride layer is placed directly on the silicon, and one oxide layer is placed between the nitride and the top electrode. This further enhances the effective k value of the dielectric stack, but the only way to further improve performance with nitride is to use area enhancement techniques.

One area enhancement technique that has been proposed is to give trench capacitors a bottle shape. Researchers at IBM are developing a method in which a 5 µm deep trench is formed by reactive ion etching (Fig. 2). The trench is then partially filled with a resist material, and an oxide collar is grown on the inside of the opening. After the resist material is removed, an isotropic silicon etch is done to give the trench a bottle shape. The researchers claim 5 µm deep trenches can be made with openings as small as 0.10 µm.

Fig 1 One proposed roadmap for DRAM materials features tantalum pentoxide through to the 100nm/4 Gb node. (Source: Applied Materials)

Nitride stacks can only enhance the memory cell's capacitance by about a factor of two over the use of oxide. Even with area enhancements, new materials will be needed.

Other oxides

Tantalum oxide (Ta₂O₅) is generally accepted as the next material for use in memory capacitors. With a k value of 25, it provides a potential 4-to-6x increase in capacitance over oxide, depending on the barrier material scheme that is used. Alumina, Al₂O₃, also is under consideration as a dielectric, and as a component in giant magnetoresistive (GMR) memory cells. With a k value of about 9, alumina provides little electrical advantage over silicon nitride, but it may provide material advantages since it requires no barrier with silicon. In fact, alumina can be used as a barrier material, and some believe it to be an appropriate dopant for Ta₂O₅ to control oxygen diffusion into silicon.

Fig 2 Etching the inside of trenches is one way of enhancing the capacitor's area. (Source: IBM)

Though opinions of the life of tantalum oxide vary, most seem to agree it is a one- to two-generation material. It has a useful lifespan for supplier companies that have tools ready now (Fig 1). One problem with Ta₂O₅ is that it requires a barrier material, which will reduce the stack's effective k value. Another problem is oxygen diffusion during anneal. An anneal must be done to crystallize the Ta₂O₅ into the proper structure. Care must be taken to grow and anneal the film with minimal interdiffusion. (See Annealing of High-k Dielectrics, p. 82.)

One proposed method is to deposit a nitride layer as a barrier between silicon and Ta₂O₅, and a TiN barrier over the Ta₂O₅. The nitride layer is chosen to handle the anneal temperature for the Ta₂O₅ film, while TiN is more effective as an oxygen diffusion barrier. This is the approach Applied Materials plans to use for its MOCVD approach.

Precursors for MOCVD of Ta₂O₅ under study are TATDMAE (Ta(OC₂H₅)₄(OCH₂CH₂N(CH₃)₂)) and TAETO (Ta(OC₂H₅)₅). Both are reacted with oxygen at a temperature of 4507C and a pressure in the 1-4 Torr range, and deposition rates seem to be independent of precursor.

According to Mehrdad Moslehi of CVC (Rochester N.Y.), pulsed DC plasma sputtering and ion beam deposition are useful methods. For plasma sputtering, Ta atoms sputtered from the target react with oxygen in the plasma to form the oxide. Also, an oxide can be allowed to form on the target in the 'poisoned' deposition mode. For ion beam deposition, a broadbeam argon ion source sputters the Ta atoms from the target, and a broadbeam oxygen ion source is aimed at the wafer to form the oxide. An oxide target can also be used for ion beam deposition, and an optional argon ion source can be aimed at the wafer to control microstructure.

Atomic layer deposition recently has surfaced as a viable technology.² It relies on chemisorption of precursor gases that are introduced one at a time. One reactant is exposed to the wafer, and a monolayer is formed. That first reactant is flushed out, and a second reactant is added, which deposits another monolayer. This technology is suited to deposition of composite materials, such as alumina, Ta₂O₅ and possibly some of the other materials described below.

According to Ernst Granneman of ASM (Bilthoven, Netherlands), the key to making this technology viable is small chamber design. 'Since you only need to saturate the wafer with the precursor, you don't have to design the chamber for uniform reactant coverage. So you can make the chamber very small, 4 mm high, and run as many as four cycles in one second.'

Since this technology depends on chemisorption, deposition temperatures can be low, with the expectation of good step coverage because of the single-layer mechanism. The fact that precursors are only present one at a time allows the use of more aggressive chemistries, which also can lead to reduced deposition temperatures. In addition to ASM, Genus is offering this type of process.

Paraelectric perovskites

After tantalum oxide, DRAMs can use perovskite structure materials with k values in the hundreds. Perovskite materials exhibit ferroelectric behavior when held below their Curie temperatures, and paraelectric behavior when above that temperature.³ For some compositions of these materials, antiferroelectric behavior also is possible, but for the purposes of memory capacitors, those compositions are avoided.

For both the paraelectric and ferroelectric states, polarization occurs through the mechanism shown in Fig. 3. Movement of the tetravalent and oxygen ions provides the polarization. The differentiation between the two states comes from the material's ability to store a polarization when in the ferroelectric state. In the paraelectric state, the material simply acts as a very high-k dielectric material. Though materials in the paraelectric state can be used in DRAMs, ferroelectric materials require a different kind of circuit design.

The most popular of the high k materials is barium strontium titanate (BST), Ba_xSr_1-xTiO₃. The Curie point varies linearly with composition, having a value of about 1207C for x = 1 and about -2207C for x = 0.⁴ The strontium is added to reduce the Curie point below room temperature, which ensures paraelectric operation. Also, the dielectric constant and its sensitivity to temperature vary with composition. Barium/strontium composition is an important parameter in BST's use in memory capacitors. The dielectric constant of the paraelectric also can be very sensitive to temperature near the Curie temperature, where it has the highest value.

Depositing a stoichiometric film is also very important for the electrical properties. Since the motion of titanium ions is key for the dielectric property of BST, titanium vacancies and interstitials degrade the dielectric properties. Studies have shown a slight excess of titanium is better than a slight shortage, so approaching the correct stoichiometry from the side of excess titanium is desirable.

Oxygen is easily removed from the material in the presence of a reducing atmosphere, such as a forming gas anneal, which degrades the material's dielectric properties. Oxygen anneals can ensure a proper oxygen content, and the appropriate choice of top electrode materials can protect the dielectric from reducing in subsequent processing.

The perovskite structure is important to the material's dielectric properties. Various methods are being used to preserve that structure during deposition, including RF sputtering, MOCVD followed by an anneal and single atomic layer deposition.

RF sputtering requires an appropriately designed composite target. Since the sputtering rates for different elements vary, the useful lifetime of a single sputtering target is not likely to be very long.

For RF sputtering methods, the underlying electrode material is very important. According to Elliot Philofski, former CTO of Ramtron (Colorado Springs, Colo.), 'BST likes to form good crystal structure on platinum.' Platinum does not oxidize, so it can withstand the necessary oxygen anneals. It is necessary to use a metal-insulator-metal (MIM) structure with certain metals or conductive oxides to prevent oxygen diffusion into silicon, and platinum seems to provide the best benefit as a bottom electrode. Philofski added that BST won't have the right crystal structure if grown on silicon.

One big challenge for using perovskite materials is that they are very difficult to etch. Many say etching these materials is really a sputtering process in an argon plasma. The use of chlorine or fluoride chemistries provides limited aid, since most of the etch products are non-volatile solids. These products may be removed more easily by argon bombardment than the dielectric material can be.

One approach specifically mentioned in the 1997 National Technology Roadmap is dual-frequency high-density plasma. Separate RF power sources are used for the plasma and wafer biasing.⁵ On this approach, Jim McKibben of Tegal said: 'Dual frequency gives you two knobs. One allows you to control the ion density at the wafer plane, and the other one allows you to control the ion energy, the bombardment energy. And these materials are very, very difficult to etch. And by having these two abilities to either bombard it with a chemical-density nature, or the physical-energy nature, you can change etch profiles.'

Masking for the etch process is another challenge. The material to be etched must be physically attacked, while the materials that are masked off are etched more easily.

Ferroelectric materials

Ferroelectric memories are a form of non-volatile memory in which a polarization is stored. In the ferroelectric state, the two states (actually six) shown in Fig. 3 are energetically favorable to the symmetric, unpolarized state. These spontaneous polarizations in the <100> directions actually correspond to tetragonal rather than cubic symmetry for the crystal. As the temperature drops further below the Curie point, transitions to monoclinic (<110>) and rhombohedral (<111>) phases can occur. For memory applications, a material with tetragonal symmetry in the operating temperature range likely will have the best polarization characteristics.

Fig 3 The basic perovskite structure lends itself to polarization by ionic motion.

In an arrangement where the cells are aligned, and all applied electric fields are along the z-axis, the cells are bistable polarization storage elements. An applied field can change the state, but no field is required to maintain that state. The sensing and changing of polarization states is different from the sensing and changing of stored charge done in DRAMs, so different circuitry is required.

Among the candidate materials, lead zirconate titanate (PZT), PbZr_y Ti_1-yO₃ seems to be the most popular, though many materials show promising results. Another material under consideration is strontium bismuth tantalate (SBT), SrBi₂Ta₂O_9,,which is a layered perovskite. Bismuth oxide layers reside between perovskite layers, which helps stabilize the stored polarization.

Ferroelectric materials are also piezoelectric. Mechanical stress affects the polarization properties, and applied fields can affect the mechanical stress. Care must be taken to control film stress to keep the polarization storing properties consistent. Also, some materials, depending on the composition, can be at a border line between phases, which gives them highly sensitive piezoelectric characteristics. For example, PZT with y P 0.55 is on the border between tetragonal and rhombohedral, and it has a high piezoelectric modulus.⁴

Electrode materials

The perovskite materials require a special set of electrodes, based on metals found near the middle of the periodic chart such as ruthenium (Ru), iridium (Ir) and platinum (Pt). Oxides of these metals also are conductive, making them candidates for inclusion in the electrode stack.

Conductive oxides can improve the capacitor's reliability by reducing its fatigue. Imperfections such as oxygen vacancies can migrate and collect at the electrode interfaces after a number of cycles. This can lead to trapped charge screening and other effects that degrade the capacitor's operation. Philofsky of Ramtron said, 'Eventually, oxygen vacancies will pile up at one of the interfaces, and you lose switching If you use a conductive oxide, they don't pile up; they go across the interface, and you get more life.'

Platinum is desirable as a bottom electrode in MIM capacitors because of the growth characteristics of BST film on top of it. If used as a top electrode, though, it may catalyze reducing reactions between forming gas and the underlying dielectric. Ruthenium and ruthenium oxide (RuO₂) are relatively easy to etch, and they may see use as a top electrode, though one of the products of the etching process, RuO₄, is both flammable and toxic.

Fig 4 Magnetic memory technologies with promise include pseudo spin valve (a) and magnetic tunnel junctions (b).

Magnetic materials

Magnetic memory technologies hold a great deal of promise because they are non-volatile and have very fast access times. The main challenges are low temperature requirements and extreme deposition challenges. Two promising technologies are pseudo-spin valve (PSV) and magnetic tunnel junction (MTJ).

PSV uses the giant magnetoresistive (GMR) effect found in read-write heads.⁶ Fig. 4a shows the basic PSV structure. The magnetization is stored in the thick magnetic layer. The cell is read non-destructively by passing a current though the word line over the stack, and passing both positive and negative currents through a digit line underneath. The combined magnetic field from the two currents is enough to switch the thin magnetic material, but not the thick layer. When the magnetizations of the two magnetic layers are parallel, the resistance through the stack is reduced.

The challenge for this technology is depositing the ultra-thin non-magnetic layer. A thickness of about four atomic layers is required to achieve the necessary resistance ratio between the on and off states. One method under evaluation is to deposit a two-atom-thick layer of aluminum, followed by exposure to oxygen, to make the required alumina film. Another possibility is ALD. Depositing a 3 nm layer of copper has been done for GMR heads, but reasonable uniformity for such a film on a 200 or 300 mm wafer will be a challenge.

A representative MTJ structure is shown in Fig. 4b. The materials used are the same ferrite-type materials found in hard disks. The read and write mechanisms are the same as for hard disks, except that the memory space is divided into discrete cells.

Micromem Technologies has developed a magnetic memory technology called MAGRAM. The company has not released information about the materials its technology uses, but since they claim to be able to build memory on glass plates, it must be a low-temperature process.

All these magnetic memory technologies require low temperature processing. It has been shown that memory performance degrades when the materials are heated above 300°C. It is still possible to incorporate these memories into CMOS devices, if the memory cells are created last in the process.

Conclusion

Though oxide and oxynitride dielectrics still have some life left, high-k materials soon will have to replace them. Tantalum pentoxide can provide effective k values in the 20-30 range, and it can last as far as the 100 nm/4 Gb technology node. BST is the first of the perovskites likely to achieve volume production in memory capacitors, though its k value, which is in the hundreds, can be very sensitive.

Ferroelectric materials are finding use in niche markets such as smart cards. Significant hurdles, such as high thermal budgets in oxygen ambients and the need for highly aggressive etching approaches, can impede its use in production volumes. Magnetic memory technologies hold the same promise for non-volatility that ferroelectrics do, but they require low temperature processes. They provide another challenge in that some ultra-thin films must be grown with a high degree of uniformity across the wafer

References

1. D. E. Kotecki, High-K Dielectric Materials for DRAM Capacitors, Semiconductor International, November 1996, pp. 109-116.
2. P. Singer, 'Atomic Layer Deposition Targets Thin Films,' Semiconductor International, September 1999, p. 40.
3. C. Kittel, Introduction to Solid State Physics: Sixth Edition, John Wiley & Sons, 1986.
4. F. Jona and G. Shirane, Ferroelectric Crystals, Dover Publications, 1993, and references cited therein.
5. National Technology Roadmap for Semiconductors, SIA 1997.
6. J. Baliga, 'GMR Read-Write Heads Yield Data Storage Record,' Semiconductor International, February 1998, p. 38.

Annealing of High-k Dielectrics

Pravin Narwankar, Annabel Nickels and Michael Buss, Applied Materials Inc., Santa Clara, Calif. The two high-k materials of greatest interest for DRAMs are crystalline ceramic oxides, Ta2O5 and BaxSr1-xTiO3 (BST), whose large dielectric constants are the result of the strong ionic polarization. To obtain the high k necessary for high-density DRAMs, the films must be free of impurities, have correct stoichiometry, and be crystalline. However, these films are deposited using metal-organic chemical vapor deposition (MOCVD) process at low temperature (400ºC-500ºC) to meet stringent step coverage requirements. The films are then annealed to achieve the desired capacitance and leakage current. Annealing of the films accomplishes three things. First, annealing removes trace impurities in the films. Thermal desorption spectroscopy shows that CH4 and H2O gases diffuse out of Ta2O5 films at ~600ºC. Similarly, CO2 diffuses out of BST at temperatures as high as 900ºC as a result of the breakdown of metal carbonate impurities in the as-deposited film. The removal of impurities reduces the leakage currents and increases their capacitance by increasing the film densities. Second, annealing balances the stoichiometry of the films for optimal electrical properties. For Ta2O5, as-deposited films are oxygen deficient and resistive (non-insulating). By annealing in oxygen, the correct stoichiometry is obtained. For BST, different researchers have reported improved electrical properties using both oxidizing and reducing anneals. Third, annealing crystallizes the high-k film. As deposited, the films are amorphous and do not have the requisite microstructure to yield the desired electrical properties. Temperatures of ~800ºC are required to crystallize Ta2O5 and ~700ºC to crystallize BST. Annealing of high-k films must be carefully controlled for two reasons. First, the total thermal budget of a semiconductor device is limited. Exposure of the device to high-temperature anneals for extended periods can ruin the device. Second, the annealing process can affect the substrate beneath the dielectric. For example, in Ta2O5 metal-insulator-silicon (MIS) structures, the bottom electrode consists of ~20 Å SiN on polycrystalline silicon. During annealing, oxygen diffuses through the Ta2O5 and reacts to form low-k SiO2 at the interface. As anneal process time increases, the capacitor stack storage capacity decreases. There are two processing techniques that achieve all the benefits of annealing while minimizing the impact on the device. The first is to rapidly ramp the temperature for both ramp-up and cool-down. This minimizes the impact on the thermal budget and reduces the time during which oxygen can react with the substrate beneath the dielectric. The second technique is to deposit the high-k dielectric in two steps, annealing after each deposition. Since annealing these films is essentially a diffusion limited process, reducing the thickness of the film by a factor of two can reduce the anneal time for each step by a factor of four. For systems with rapid temperature ramp capability, this results in further savings in the thermal budget and reduction of substrate oxidation. Better capacitance with shorter anneal times and equivalent leakage performance is obtained by using the two-step deposition and anneal technique.