SOI Comes of Age
Ruth Dejule, Associate Editor -- Semiconductor International, 11/1/1999
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At a Glance | | |
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Material quality
Silicon-on-sapphire preceded SOI in the early '60s. Fifteen years later, the bond and etch-back was developed, where two silicon wafers, one with a grown oxide, are bonded and the back of one etched, leaving behind thousands of angstroms of silicon on oxide. Over the past couple of years, the defectivity of SOI materials has improved dramatically, particularly for those defects that act like light point-scattering points. For many SOI defects, when etched with hydrofluoric acid, the acid penetrates through to the buried oxide, making the defects very vivid. General cleanliness has improved the wafer surface, preventing particles from infusing into the layers. Proper crystal growing techniques can minimize crystallographically oriented particles or pits (COP), voids occurring in the bulk Czochralski growth. The voids are octahedral (eight-sided, double pyramids), 1000 to 2000 Å in diameter. The growth of an epitaxial layer effectively fills the voids that remain on the surface.
Of the two basic SOI technologies, separation by implanted oxygen (SIMOX) and bonded wafers, SIMOX historically has had more surface roughness, crystalline defects, silicon inclusions and pinholes; bonded wafers still have crystalline defects but have smoother interfaces and no buried oxide inclusions. Due to state-of-the-art cleaning and handling, and improved cleaning and wafer bonding equipment, in the past four years defect densities in bonded wafers have been reduced dramatically -- on the order of 400X (Fig. 2), noted Mike Mendicino, manager of SOI technology development for high performance applications at Motorola. Overall, the defect density of the lower-dose, 2000 Å buried oxide SIMOX wafers and recent bonded wafers is not si gnificantly different from bulk silicon wafers, he added.
SOI parameters
Silicon and SiO2 layers on a bulk silicon substrate provide electrical isolation that reduces parasitic capacitance and accompanying latch-up. The result is higher dynamic frequencies and lower power consumption. SOI wafers are generally classified as 'thick' (a top silicon layer L1.5 µm) and 'thin' (thicknesses l0.5 µm). Produced by companies such as SEH and Mitsubishi Materials, thick layers are used in bipolar, MEMs and plasma displays; thin are targeted for digital CMOS technologies. The relative layer thicknesses can impact device performance. Thinner top silicon layers on the order of hundreds of angstroms are generally considered fully depleted with intimate electrical interaction between the buried oxide and operation of the device. This affords higher device speeds, but processing such thin layers can be difficult, and circuit design becomes more complex because of floating body effects. The silicon thickness also must scale with channel length. Whereas, in thick, partially depleted layers, 1000 to 2500 Å of silicon, the oxide serves merely as isolation. Because of enhanced performance, digital CMOS and memory and logic devices are ta rgets for thin, fully depleted SOI layers. Thicker, partially depleted layers are typically used today.
SIMOX
SIMOX is based on the established ion implant technology. A silicon dioxide (SiO2) layer is formed by implanting oxygen through the top surface of a standard bulk wafer. Maximum oxide thickness is typically 4000 Å. Thicker layers require higher doses, and crystalline damage to the top silicon increases with the dose. To maintain a crystalline surface and minimize the creation of dislocations, wafers are held at temperatures
L 500°C during implantation.
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| Fig 1 The PowerPC 750 chip, grown on SOI wafers (bottom), contains 6.32 million transistors. (Source: IBM) |
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| Fig 2 Average defect densities for both SIMOX and bonded materials and SOI circuit yield relative to bulk silicon have significantly improved, making mainstream SOI products feasible. (Source: Motorola) |
Compared to conventional ion implanters used for doping wafers, oxygen implanters like those manufactured by Hitachi and Ibis Technology (Danvers, Mass.) have higher oxygen dosages, by a couple of orders of magnitude, on the order of 1x1017 to 2x1018/cm2. This translates into long implant times, up to 8 hrs (standard implants are on the order of minutes). To compensate for poor throughput, beam currents can be as high as 55 mA, compared to a couple of milliamps for dopant implants. But higher beam currents lead to contamination problems. One approach to improving throughput is by going to thinner layers. For example, 'a reduction in buried oxide thickness from 4000 to 1000 Å would triple throughput to 60 wafers per day,' said Michael Alles, director of marketing and applications engineering at Ibis. And thinner layers may have device performance advantages. While current state-of-the-art buried oxide layers are 0.4 µm thick and top silicon 0.2 µm (due to current 200 kV implanter designs), the Roadmap is calling for half that, 0.2 µm and below. The fact that operating voltages are being reduced means a 0.2 µm layer is acceptable as long as the integrity of the oxide is sustained, contends Alles. Implants through the top single crystal silicon produce stacking faults and lattice defects, which must be repaired with 8- to 12-hr anneals at 1300°C.
Studies are underway to improve the quality of thinner layers. Jointly developed by Komatsu, Nippon Steel, NTT and Hitachi, internal thermal oxidation (ITOX) improves the quality of thin buried oxides by annealing the wafer at ~13007C in an oxygen ambient, following oxygen implantation. The top surface is oxidized, and some oxygen penetrates the top surface and oxidizes silicon inclusions in the buried layer and the bottom of the silicon film. Results have indicated better-quality SOI wafers. Other processes for thinner layers use various implant energies or multistep processing to improve the quality of the buried oxide layer, according to Alles. The tradeoffs are among implant dose/current and device performance; temperature and crystalline quality. The common factor is cleanliness. Higher dosage, longer implants and higher temperatures can increase the introduction of contaminants into the layers.
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| Fig 3 SEMs of an ELTRAN bonded wafer (top) demonstrate flattening of the surface when the wafer is hydrogen annealed (bottom). (Source: Canon) |
Contamination control can be enhanced through the implant tool design. A microwave ion source is used to create the plasma. Oxygen ions then are extracted from the plasma and accelerated toward the wafer. To minimize metal contaminants, it is important to use as few metal-containing parts as possible or coat the components in the beam path. Making sure the beam path from the source to the wafer is as indirect as possible can also effectively reduce the number of particles that reach the wafer, according to Jim Manos, marketing manager for Hitachi America Ltd. (Carrollton, Texas).
Uniformity is another important issue. Magnetic beam scanning may influence beam properties such as beam profile and current distribution because the lens action of a scanning magnet changes depending on the beam position, Manos said. By mechanically rotating the wafer in the vertical plane and moving it back and forth in front of the beam, Hitachi implanters can achieve buried oxide uniformities to within ±20 Å, he said.
Thin oxide SIMOX wafers are anticipated to be less than $200 per 200 mm wafer, Alles said. Though still 3 to 4 times the cost of bulk, this is 2 to 3 times better than projections five years ago. The limitation of SIMOX for implant oxide layers l 0.5 µm makes bonded wafers the method of choice for high-voltage applications.
An alternative implantation method to manufacture SIMOX-like wafers uses Plasma Immersion Ion Implantation (PIII) technology to implant the oxygen. This process, called Separation by Plasma Implantation of Oxygen (SPIMOX), is being investigated through a collaboration between Silicon Genesis (SiGen, Campbell, Calif.) and Komatsu Electronic Metals (Tokyo).
Bonded wafers
Until 1995, SOI material quality was poor; defectivity was very high, prohibiting people from designing and successfully building large circuits in SOI. The emergence of new layer transfer technologies has generated renewed interest in bonded SOI wafers. These technologies include a bonded technique from SOITEC; another from SiGen, which uses an alternative method of layer separation; and epitaxial layer transfer (ELTRAN) from Canon. These approaches are replacing the original bond and etch-back technology, which used two wafers, had high defectivity and was cost-prohibitive, according to Motorola's Mendicino.
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| Fig 4 The new, fully automatic SOI wafer facility in Bernin, France, houses 15,000ft2 of Class 1 and Class 10 cleanrooms with self-contained mini-environments. (Source: SOITEC) |
The bonded-wafers approach consumes essentially one wafer. A thermal oxide is grown on one wafer and hydrogen implanted through to a predetermined depth. This is bonded to a second silicon wafer, the handle wafer, and upon heating, tiny bubbles form and the wafers split apart along the plane at which the peak of the hydrogen implant concentration was placed. A few thousand angstroms of silicon are thus transferred to the handle wafer. The top surface is subsequently polished, and the wafer is annealed at 1100°C. SOITEC creates microvoids with conventional hydrogen implants. After splitting, the handle wafer can be reclaimed for future use.
Unlike the other SOI techniques, Canon's ELTRAN process begins with a silicon substrate containing a porous silicon layer upon which an epitaxial silicon layer is grown, followed by a thermally oxidized layer. The seed wafer is bonded to a handle wafer, and grinding or splitting exposes the porous silicon. This layer is subsequently etched to the epitaxial silicon, and a hydrogen anneal finishes the surface (Fig. 3).
Reflecting the growing demand for SOI wafers, SOITEC SA, a $50M, fully automatic facility (Fig. 4) in Bernin, France, currently produces 200,000 wafers per year, and capacity is expected to double next year. To meet industry demands, 300 mm SOI wafers have been demonstrated and will be in production in 2001, according to Andrew Wittkower, president of SOITEC USA (Peabody, Mass.).
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| Fig 5 This rather aggressive forecast reflects the 11 fabs in Japan and 12-15 in the U.S. and Europe due to ramp up SOI device production over the next two years. (Source: Rose Associates) |
'The edges in SOI wafers, where the silicon film and buried oxide terminate, have been the source of a lot of headaches,' said Mendicino. For bonded wafers, where the top silicon layer is derived from a different wafer, that edge can be jagged or discontinuous. However, in SIMOX the edge is always clean because the implantation extends off the edge of the wafer. Old bonded technologies had edge exclusions of 7 or 8 mm, but new bonded techniques are considerably better, in the 3 mm range. SIMOX, however, has the same 2 mm edge exclusion as bulk wafers.
Similar to thin oxide SIMOX, unibond prices are expected to be less than $200 per 200 mm wafer, noted Wittkower.
Manufacturability
For the past five or six years, companies like Analog Devices, Harris Semiconductor and Honeywell have been producing SOI devices in moderate volumes. These niche products, originally developed for defense and space applications, are ideal for SOI structures because of resistance to radiation. The small volume of silicon, a few thousand angstroms isolated from the substrate, effectively limits absorption of high-energy particles and resulting currents, which could upset memory states. Thus SOI is appropriate for radiation-hardened devices, such as Honeywell's 0.35 µm CMOS static RAM, and gate arrays. Mitsubishi Electric was first to announce a product using partially depleted SIMOX, a gate array product designed for low voltage. Thick layer applications to flat-panel displays and MEMS also are increasing rapidly.
Last year, SOI entered into a mainstream manufacturing line at IBM's Burlington fab. Microprocessors similar to 0.22 µm bulk CMOS chips with copper interconnects are fabricated, but the SOI version is 25% faster at 500 MHz. Using a SIMOX processed wafer, the microprocessor is a partially depleted device with 1900 Å of top silicon and 3500 Å oxide.
In manufacturing SOI devices, the primary difference to bulk silicon is in circuit design, according to Ghavam Shahidi of the IBM Semiconductor Research and Development Center. For example, to eliminate floating body effects, a body-tie connects all the transistors to form a common ground. But processing is the same. The same equipment is used though the antireflective coatings require minor tweaks, implant conditions are modified and isolation processes are a bit different. The same metrology tools are used but are operated in a different regime. Silicon clusters residing in the oxide can be 'seen' when inspecting the top silicon layer, making it hard to distinguish between good and bad defects. At IBM, a special filter is added to the defect detection tool or the sampling wavelength changed to inspect only the top silicon layer. In addition to tool modifications, special software also accompanies the introduction of SOI into production. The biggest challenge, noted Shahidi, is making wafers that consistently have low defect densities and uniformities.
While the reduction of defect densities has posed a challenge in terms of yield, it's not clear whether the cause is SOI defects or the circuit design, Shahidi said. 'On some of the products, we see better yields on bulk silicon, but on some we see equivalent yields.' Currently, the microprocessors are being debugged and the design tweaked.
Conclusion
Bonded wafers provide a smoother interface; SIMOX provides better layer thickness control and scalability. In the U.S. and increasingly in Asia, there is a tendency toward partially depleted devices. But whatever the approach, 'SOI may be more important than copper for staying on the technology Roadmap, or at least at the same level,' said Shahidi. Copper speeds up the back end (so do low-dielectric materials); SOI does the same for the front end.
Entry into mainstream production will depend on the supply, quality of material and cost. According to Daniel Rose, president of Rose Associates (Los Latos, Calif.), some of the new SOI techniques may be capable of 60 wph, significantly impacting price. He forecasts $3.50/in.2 by 2005 (Fig. 5). Once the SOI decision is made, the cycle time to generate the infrastructure, design and technology know-how may be three to five years, according to Motorola's Mendicino. Product learning, reliability and packaging further add to development time. But to the fabs like IBM and Motorola, SOI is an important strategic part of their roadmap.
