Solving the Integration Challenges of Low-k Dielectrics
Laura Peters, Senior Editor -- Semiconductor International, 11/1/1999
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At a Glance | | |
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A strong desire for extendibility to future generations also drives material selection. Extendibility allows simpler transfer of etch, polishing and cleaning processes. The clearest path to lower k values involves adding pores or voids. 'If you're going to use a porous material, there's a tremendous driving force to extend your densified material to its porous version; that's the motivation here and everywhere,' said Dr. Robert Miller, manager of advanced organic materials at IBM's Almaden Research Center (San Jose, Calif). For this reason, selection in the k = 2.6-2.8 realm is influenced by the likelihood of being able to integrate porous versions.
When companies transitioned from SiO2 dielectric (k = 3.9-4.1) to CVD of fluorinated oxide (FSG, k = 3.6) and spin-on of hydrogen silsesquioxane (HSQ, k = 2.9), they encountered certain integration challenges. For FSG, the fluorine must be tightly bonded in the CVD film as fluorine interaction with barrier layers causes 'blistering,' where volatile TaF compounds form at high temperatures. FSG fuels today's 500 MHz microprocessors with copper damascene while also meeting gap-fill requirements in aluminum interconnects. Using PECVD of FSG, 'we found that dielectric constant is limited to around 3.7,' said Wilbert van den Hoek, executive VP of integration and advanced development at Novellus (San Jose, Calif.), 'while the k value in damascene is around 3.5 because zero bias can be used to deposit a more stable CVD film.' Using HDP-CVD of FSG, Farhad Moghadam, VP and general manager of Applied Materials' Dielectric CVD Division, explained, 'with the installed base of HDP FSG used in today's 500 MHz microprocessors we've learned how to extend FSG capability to 3.3 by monitoring FSG composition and the hydrogen content in the film.' Moghadam estimates 20% of the company's FSG installations are depositing 3.3-3.4 k value films. HSQ films, typically deposited using Dow Corning's FOx material, require dielectric barriers and capping layers to prevent moisture uptake in the film, and the integration sequence must be optimized to prevent cracking.
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| Low-k dielectrics require holistic optimization of etching, CVD, CMP and metalization processes. (Source: Applied Materials) |
Device challenges
Low-k dielectric integration in a dual-damascene structure (Fig. 1) requires film compatibility with all etching, stripping, CMP, lithography and metalization processes. The low-k material must demonstrate high thermal stability, low coefficient of thermal expansion, a stable and continuous (isotropic) k value, and low outgassing. A high glass transition temperature (Tg) is needed to prevent dielectric flow or 'creep.' Also essential are adhesion to TaN and a high-selectivity etch chemistry to etch stops and barriers. Mechanical stability to undergo packaging is crucial. 'If you look at development strategies, the last thing you want is to have your critical step be the last one. With low-k materials, it's the multilayer build and packaging that really provide the ultimate test,' said Tom Rosenmayer of W.L. Gore & Associates (Elkton, Md.).
None of the current low-k candidates dissipates heat as well as SiO2, possibly resulting in electromigration and reliability concerns. 'You need to achieve better reliability with respect to failures per unit length of interconnect due to the fact that the amount of interconnect on the chip is growing geometrically,' explained Winebarger. 'This improved unit reliability is a difficult challenge given low-k dielectrics' diminished mechanical characteristics, device scaling placing lines closer together, and the potential interaction between the low-k dielectric and the cladding material around the copper interconnect.' Even moderate differences in thermal conductivity can be an issue. Unfortunately, such issues can only be tested once 6-level metal devices or test vehicles are manufactured and tested for stress migration and electromigration.
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| Fig 1 Integration of low-k materials into trench and via levels requires interface engineering with etch stops, cap layers and copper barriers. |
At the same time a company's dual-damascene architecture influences low-k dielectric selection. Most companies favor via-first approaches because they make the best use of copper and are simpler than other schemes. 'There are a lot of questions: Do you use a buried hard mask, no hard mask, single or double hard masks? Everyone has their own technique,' said Miller.
Today's choices
Like the transitions to FSG and HSQ, the step to lower-k materials (2.6-2.8) offers spin-on and CVD options. 'Due to the significant amount of integration work with these materials, people want to choose a material that will be widely used in the industry to obtain the benefit of learning from the tool companies,' explained Jack Braley of Dow Chemical (Midland, Mich.). Though there are leading candidates, there is little consensus on the 'material of choice' for 0.13 µm devices.
Spin-on options appear to be more extendible as suppliers develop porous versions of organic polymers, the most promising of which are polyarylenes and polyarylene-ethers such as SiLK from Dow Chemical (Fig. 2) and FLARE from AlliedSignal. 'I can see extendibility in that area that I don't see in CVD films,' said Miller. Bolick said AlliedSignal is pursuing a non-porous approach to extending the FLARE product below k = 2.7, while also pursuing a parallel low-k effort with HOSP, a hybrid organic siloxane polymer film, which is 'closer to a traditional oxide and has a similar chemistry to our discovery material, Nanoglass.'
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| Fig 2 Damascene etch in SiLK material uses oxide caps and a nitride etch stop. (Source: Dow Chemical) |
The potential move to organic polymers could reduce the number of etch chambers by up to 25%, according to Braley. 'You don't have to clean the chamber after each wafer is etched. This, combined with a higher etch rate, can reduce the number of etch chambers significantly.' He added that ARC layer also can be eliminated by tuning the hard mask.
The 2.6-2.8 k CVD films, often referred to as OSGs (organosilicate glasses), are carbon-doped SiO2 films, offered commercially as Black Diamond from Applied Materials (Santa Clara, Calif.), CORAL from Novellus and Aurora from ASM (Phoenix). The k value of these low-density films is reduced by adding methyl groups to the SiO2. Tetramethylsilane or trimethylsilane liquid precursors are provided by Dow Corning or Schumacher (Carlsbad, Calif.). Figure 3 illustrates etching of CORAL via and trench levels using Lam's dual-frequency capacitive etching system.
As-deposited OSG films are hydrophobic, and etching, stripping and cleaning processes must be precisely tuned to keep the material hydrophobic. If methyl groups are removed, the film becomes hydrophilic -- increasing k value and mak ing it subject to moisture contamination. Another potential problem is via poisoning, caused when silicate-containing materials outgas after depositing high-temperature barrier films.
One of the most significant breakthroughs in dielectric barrier layers has been the recent development of SiC-based CVD films that yield a dielectric with a minimum k of 4.5, replacing the nitride (k=7+) barrier. Applied Materials and Novellus offer SiC-based CVD processes. Applied claims a 35% capacitance reduction using OSG low-k and SiC-based barriers versus SiO2 dielectric with nitride barriers. Its BLOk film offers twice the etch selectivity of nitride layers when etching oxide-like films such as FSG and Black Diamond. Increased selectivity increases via CD control during etch (Fig. 4). SiC-based films also adhere better to FSG than nitride. 'A common integration scheme today uses 500 Å of BLOk between the trench and via, replacing a 1000 Å nitride film to lower the overall k value,' said Applied's Moghadam. 'We see two generations of 0.13 micron devices -- one using FSG and BLOk and the second, high-performance going to k less than 3.0 with Black Diamond and BLOk.'
The dielectric constant of OSG films can only be reduced to about 2.5 by adding methyl groups. The porous route and/or chemistry changes will be required to extend these CVD films further. Preliminary work on second-generation Black Diamond and CORAL films has been performed. Moghadam warns, 'I think there's going to be an exponential increase in integration issues as you go to k less than 2. We are investigating templated oxide approaches to address some of the issues related to porous oxide, including void size distribution and mechanical strength.'
Earlier this year Novellus abandoned its Parylene low-k project, involving a fluorinated amorphous carbon film. The company said Parylene was fully integrated yet required additional process steps that, together with high precursor cost led to a higher cost of ownership than was commercially viable.
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| Fig 3 Trench and via etching of CORAL film demonstrates good selectivity to photoresist (5:1) and nitride (10:1). (Source: Lam Research and Novellus) |
Ultralow-k
At k< 2.2, the playing field narrows to only a few organic and inorganic materials, either highly fluorinated polymers or porous films. SEMATECH is evaluating a handful of spin-ons, mostly porous materials -- a couple of organic polymers and several silica films.
From an R&D standpoint, Miller suggests 'bringing up both hard, brittle silicon-containing materials and softer, tougher organic thermosetting polymers in both dense and lower-k porous versions as quickly as possible. Since these different material classes are not likely to suffer from the same material-related integration flaws, early assessment of both could help resolve the challenges of integrating porous materials.'
Engineers are reluctant to work with highly fluorinated films due to experience with some low-k materials where unstable fluorine attacked the copper barriers. But the low-k properties of fluorinated films make them attractive. 'If one could figure out how to incorporate fluorine into these materials in a stable manner, it could lead to appreciably lower-k materials with better thermal budget than we have now,' said Winebarger. Mike Mocella, senior technical consultant for DuPont's Electronic Gases Group (Wilmington, Del.), noted an important distinction between fluorinated amorphous carbon (FLAC) films deposited by PECVD films and thermal CVD films. 'People tend to think of FLAC films as being polymeric materials, but because of the plasma deposition they are highly damaged and not uniform or orderly structures.'
'For fluoropolymers the issues are adhesion and thermal stability, but for porous materials the issue is mechanical stability,' explained Mocella. DuPont is optimizing thermal CVD of fluoropolymer films. 'If processing temperatures can be relaxed a bit to get below the 400°C range, fluoropolymer structures that begin to decompose above 400°C will become more viable,' said Mocella.
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| Fig 4 Replacing the nitride etch stop layer with BLOk SiC-based films allows improved via CD control (Source: Applied Materials) |
Currently the only commercially available, non-porous, ultralow-k film is a spin-on PTFE film from W.L.Gore. The company's Speedfilm material, with endpoint trace shown in Figure 5, has a siloxane blended into the fluoropolymer to eliminate the need for an adhesion promoter to adhere to oxides. Gore claims advantages to the k = 2.1 PTFE film include the ability to use a much thinner hard mask than is usually required with porous inorganic films and use of the same chemistry (C2F6/O2/Ar) to etch the oxide hard mask and ultralow-k film. Speedfilm's k value will be extended further using porosity and possibly replacing the siloxane component with a low-k material.
An increasingly viable approach appears to be the use of templated porous low-k materials with more regular chemical structures than randomly porous materials, leading to better mechanical stability. Schumacher soon will offer porous PolyELK (k< 2.2) organic and MesoELK (k=1.6-2.2) inorganic films. MesoELK's pore size is 3-4 nm. PolyELK has a pore size of 20 nm and a Tg of 490°C.
Etching/resist removal
FSG and HSQ etching processes require similar chemistries to those used for undoped oxide. With organic films, a hard mask is used, as the resist will etch with the low-k organic film. The etch chemistry is C2H4/O2/N2. 'The biggest issue with organics is achieving high etch rates and vertical profiles while maintaining the CD by minimizing faceting of the hard mask,' explained Ian Morey, low-k program leader at Lam Research (Fremont, Calif.). 'To achieve this we operate in a regime more characteristic of a chemical etch, minimizing ion bombardment by running at low bias.'
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| Fig 5 Endpoint for a PTFE-based polymer etched in a Lam 9100 system is identified after 20 seconds in Ar/O2/C2F6 plasma with 1800 W bias. (Source: SEMATECH) |
'One of the benefits of the CVD low-k's is you don't have to use a hard mask,' explained van den Hoek. He said low-k etching requires good pattern definition, anisotropic etching with no undercutting and high selectivity to the nitride or silicon-carbide based etch stop.
Depending on the low-k film, oxide, nitride and/or silicon carbide-based barriers and etch stops can be used. The etch stop assists patterning between the via and trench. For instance, 400 Å of oxide over 150 Å of nitride might be used for a 2.7 CORAL film to prevent copper diffusion into the dielectric 'while keeping overall k at 4.4,' explained van den Hoek.
Because oxygen-based resist ashing processes attack the low-k films with any carbon content, gentler ashing processes using forming gas (H2/N2) have been developed. 'We worked with GaSonics and Fusion using hydrogen resist removal chemistries, and both companies have gotten the ashing rates up to make the processes commercially viable,' said van den Hoek. Fig. 6 shows uniform ashing of AlliedSignal's HOSP material with an ashing rate of 8000 Å/min.
In situ strip is rapidly becoming a requirement for advanced etchers. 'In situ strip could become a process-critical issue for low-k dielectrics where you may have a solvent incompatibility,' said Mike Rice, deputy general manager of dielectric etch at Applied Materials. He added that in situ strip may improve cost efficiency.
CMP/post CMP clean
Material properties such as hardness (Fig. 7) and elastic modulus become critical for CMP processing. Hardness, or fracture toughness, indicates mechanical strength during processing.2 Polishing also tests adherence to barrier and capping layers. A hard mask/oxide cap better facilitates the CMP process.
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| Fig 6 The HOSP inorganic dielectric post-etch stripping process demonstrates 100 Å nitride loss at wafer center (left) and 140 Å loss at wafer edge (right) with 30% overetch and 50% overash. (Source: AlliedSignal and TEL) |
Rod Kistler, senior director of CMP and clean technology at Lam Research, said, 'While it is easy to polish one metal layer, the localized nonplanarity resulting from the CMP process affects subsequent levels. Dishing or erosion manifests itself in the upper levels, so one needs to optimize the entire process window to build multilevel structures more robustly.' Kistler explained how different materials have different deposition profiles -- edge thick and center thick, for instance, so 'using concentric rings we can adjust pressure gradients to different radial positions on the wafer to compensate for incoming film thickness variation.' Fritz Redeker, senior director of CMP technology for Applied Materials, commented, 'Topography control requires a precise, full-wafer endpoint that accommodates gentle overpolish conditions. Additionally, low-abrasive polish chemistries can help reduce recess and scratching of dielectrics.'
Endpoint detection is enhanced using a multi-wavelength optical detection system with the flexibility to detect a wide variety of materials.
Post-CMP cleaning needs to be optimized for the low-k dielectrics. 'We have developed post-CMP processes for OSG films that are optimized depending on the carbon ratio. This is not a trivial issue,' said Kistler. Moghadam added, 'The bonding nature is different for different materials, defined by the type of surface and how the particles are sticking to the surface, called the zeta potential.' For this reason, post-CMP cleaning in the presence of low-k stacks requires different surfactants than those used for oxide films.
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| Fig 7 A material's toughness reflects its resistance to cracking under stress. |
Porous materials may require CMP processes using lower down-force or even a complete process switch to, for instance, the chemical etch polish process offered by SEZ (Phoenix). AlliedSignal and SEZ have a strategic collaborative agreement to develop low-k planarization alternatives to remove copper with the same results of CMP, yet no risk of damage to the low-k film.
Conclusions
The successful integration of k = 2.6 low-k materials should move them into some 0.13 µm production processes. With porous versions and ultra low-k materials ahead, integration will continue to be critical.
References
1. L. Peters, 'Pursuing the Perfect Low-k Dielectric,' Semiconductor International, Sept. 1998 , p. 64.
2. Alderborn, Pharmaceutical Powder Compaction, 1996, p. 306.
