Processes Fueling GHz Operation Revealed

-- Semiconductor International, 12/1/1999

Researchers from NEC, TSMC, Hitachi and IBM recently revealed details of 0.13-0.18 µm logic processes behind the future manufacture of 1 GHz microprocessors. At IEEE's IEDM this month, NEC (Kanagawa, Japan) engineers discussed 0.13 µm CMOS technology optimization to combine high-speed RISC processors with low-power/low-standby current devices for portable, intelligent applications. TSMC also focused on the portable electronics market, revealing modifications to its 0.16 µm CPU/ASIC architecture to satisfy low standby current (I_off <3pA/µm) and ultralow standby current (I_off <0.3pA/µm) requirements. In its 'highly manufacturable 0.18 µm generation logic technology,' Hitachi provided guidelines to suppressing mechanical stress in shallow trench isolation (STI) structures while using amorphous silicon gates with RTA treatment to control drain current variation. IBM researchers used SOI CMOS to achieve 30% faster device speed than with bulk silicon.

Portable electronics requires low standby power consumption. However, standby current of logic CMOS devices increases with scaling supply voltage to obtain the same drive currents as previous devices. NEC combines two different well/channel MOSFET structures to achieve highspeed versus low-power/high-density performance, demonstrating 15 psec gate inverter delay in a 6T SRAM test device. The high-speed device has a low threshold voltage (V_t) for superior drive current using a single-well structure with p- epi layer, a local channel for NMOS and a lightly-doped n-well device for PMOS, thus reducing overall capacitance. The low-power/high-density MOSFET has a high V_t channel for low standby current (1 pA/µm) and a twin-well for narrow p+/n+ isolation. KrF lithography patterns minimum gate length of 0.11 µm and pitch of 0.36 µm. NEC minimizes reverse short channel effects by using arsenic and phosphorus mixed implant technique. Narrow (0.4 µm) p+/n+ isolation is assisted by using twin-well implantation under the STI structure.

TSMC (Hsinchu, Taiwan) explains that threshold voltage must increase to obtain low transistor off-state leakage current (I_off). But, gate-induced drain leakage and bulk band-to-band tunneling leakage limit the minimum I_off that is achievable. In addition to using super steep retrograde indium and arsenic channel implants, pocket implants and shallow low-resistivity source/drain extensions (SDEs) in its 0.16 µm CMOS process, low leakage (I_off <3pA/µm) performance is enabled by a higher channel implant dose and lower SDE implant doses. For ultralow-leakage (I_off <0.3pA/µm) devices, TSMC used a slightly longer gate length and non-retrograde channels with careful adjustment of SDE and pocket implants. PMOS device standby current can be reduced by 2X by introducing thick poly gate reoxidation.

Tokyo-based Hitachi Labs proposed a manufacturing-worthy 0.18 µm (L_eff = 0.14 µm) logic technology with controlled stress in the STI structure, cobalt salicide process, amorphous silicon gate and 6-level Al/SiOF and dual-damascene copper designs in the same layout rule. Hitachi determined that crystal defects, resulting from mechanical stress in STI structures, can be avoided by using a 60 nm radius trench corner (by optimizing trench etch recipe) to suppress dislocation formation. However, when active width of the trench is below 0.15 µm, stress exceeds critical levels due to overlap from both sides. A 20 nm pad oxide undercut suppresses this stress. Hitachi chose BF₂ implant species instead of B for source and drain implantation to prevent Co silicide agglomeration on boron-doped polysilicon during future high-temperature thermal processes. Nitrided gate oxide blocks boron penetration into the gate. To simplify gate etch, amorphous silicon is deposited followed by RTA. Gate oxide thickness is 3.2 nm.

IBM researchers in Hopewell Junction, N.Y., used low-dose SIMOX (separation by implantation of oxygen) SOI substrate, dual gate oxide, low-k interlevel dielectric and seven layers of copper metalization in a high-performance 0.18 µm (0.15 µm half pitch generation) CMOS technology. A Power4 test chip demonstrated >1 GHz performance and <8.5 psec inverter delay -- 30% faster than silicon-based 0.18 µm devices. Dual gate oxides (3.3 and 5.0 nm) allow use of 1.5 V power supply in core high-performance circuits and 1.8 V in I/O interface or specialty circuits. KrF lithography imaged 0.15 µm dimensions using 0.68 NA scanner, attenuated phase-shift masks, and significant OPC and selective linewidth compensation to minimize across-chip linewidth variation. The SOI substrate has a buried oxide thickness of 150 nm with fewer silicon defects and metal contaminants than standard dose SIMOX with lower manufacturing cost. Copper and FSG improves RC delay by 10% versus copper/SiO₂