Front-End 3-D Packaging

John Baliga, Associate Editor -- Semiconductor International, 12/1/1999

At the 3-D Packaging Symposium held in conjunction with the IMAPS show in October, 11 papers were presented on three-dimensional assembly of packaged devices and assembly of devices within packages. The presentation by Tru-Si Technologies (Sunnyvale, Calif.) depicted a wafer stacking method for performing area array interconnection among multiple dice.

The basis for the method is the company's through-silicon contact shown in Fig. 1. A trench is etched on the front side of the wafer; then layers of oxide and metal, respectively, each ~1 µm thick, are deposited. The resulting 'tub' can be filled with metal, polyimide or other material and capped with metal to leave a flat surface. Then, conventional processing of transistors and interconnects is done, and connections are made to the 'tubs.' Etching through from the back side exposes the 'tub' metal and leaves an oxide collar for insulation. An etch process is used to perform the thinning to avoid creating cracks and stress points, and to selectively remove the silicon and some of the oxide while leaving the metal untouched.

Fig. 1 Through-silicon contacts are made on the front of the wafer (a) and exposed by backside etching (b).

Fig. 2 Vertical integration starts with an interposer wafer with the eventual external I/O contacts (a). The first device wafer is bonded face-to-face with the interposer (b). Device wafers are thinned to expose the through-contacts; then the next device wafer is bonded (c).

The 3-D process starts with creation of an interposer wafer, in which through contacts are made that will be the external I/O contacts (Fig. 2). Redistribution and integration of passive devices is done on the front side of the interposer wafer, leaving bumps for connection to the first device wafer. After an 'underfill' material is applied, the first device wafer is bonded face-down to the interposer wafer. The device wafer also has through-silicon contact built in.

Next, the device wafer is thinned to expose its backside contacts, which function as bumps. After an underfill material is applied, the next device wafer is bonded face-down onto the 'bumps' of the first device wafer. According to the company, this process of bonding and thinning can be repeated indefinitely.

The final device wafer does not need through contacts, and thinning it is optional. After the last device wafer has been bonded, the interposer is thinned to expose the external I/O contacts. Singulation is the final step.

In this scheme, processing is done only to one side of each wafer to make the through contacts. Also, thinning is done in such a way that there is at least one wafer of full thickness up to the last step, so the stack has the dimensional stability of a standard wafer.

One curious aspect of the method is that little if any classical 'packaging and assembly' processing is required until the final singulation step. The underfill can be applied with spin-on equipment. Redistribution, passive integration and even the bumping on the interposer could be done with available wafer processing equipment. Bonding the wafers could be considered a packaging operation.

In addition to packing more devices into a given volume, this method provides a possible alternative to current system-on-a-chip developments. Logic and memory can be made on separate wafers, avoiding the complications and compromises of integrating them on one wafer, and bonded together to make a system in a stack.