Vertical MOSFET Demonstrates 50 nm Gates Without Lithography

Ruth DeJule, Associate Editor -- Semiconductor International, 12/1/1999

Vertical MOSFETs have the potential for higher drive currents per unit area of silicon and the control of gate length without lithography. But over the past 25 years, faced with numerous problems including poor quality gate oxides, vertical MOSFET research has been aimed primarily at specialized circuits where density is more important than performance. To achieve cutting-edge quality, researchers at Lucent Technologies' Bell Labor atories, have developed a vertical MOSFET process that uses a replacement gate approach to produce high-quality gate oxides. This, combined with mechanical scalibility to sub-30 nm gate lengths controlled precisely by a deposited film thickness, independent of lithography and etch, represents an industry first.

In previous vertical MOSFETs in which the gate length is defined through a film thickness, gate oxides typically are grown on the gate itself, rather than on the channel. The problem is that growth takes place on amorphous silicon or polysilicon gate material, causing pitting that limits the oxide's scalability. In the new vertical replacement gate (VRG) process, the silicon channel is grown selectively, and the gate oxide is formed on single-crystal silicon. A sacrificial layer, whose thickness defines the gate length, is etched away leaving a space beneath the source (see Figure), thus exposing the vertical portion of the single-crystal silicon channel. Here the gate oxide is thermally grown to thicknesses as small as 28 Å. Everything else is covered with silicon nitride. The amorphous silicon gate is then deposited by highly conformal low-pressure CVD, which 'replaces' the sacrificial layer, leaving no keyholes or voids in the gate.

A vertical replacement-gate (VRG) MOSFET is shown with 100 nm gate lengths. Gates have been demonstrated as short as 50 nm. (Source: Lucent Technologies' Bell Labs)

The pursuit of alternative dielectric materials makes the replacement gate approach particularly attractive. The gate's dimensions are defined early in the process, and the material is replaced at the end of the process, after high-temperature steps. Because many of the high-k alternative dielectrics are sensitive to high temperatures, the replacement gate approach offers a compatible process.

The Bell Labs vertical approach may prove advantageous as gate oxide thicknesses approach critical limits. The metric that drives gate oxide scaling is drive current per micron of gate width, 0.6-0.8 mA/µm. In planar devices, gate width is important because packing-density considerations limit the available gate widths. Vertical MOSFETs have a pillar or column of silicon so that the whole perimeter of the device carries the current. It may be possible to put twice as much gate width into the same area of silicon, according to Dr. Jack Hergenrother, member of the technical staff at Bell Labs. Therefore, while many factors influence the choice of gate oxide thickness, vertical MOSFETs open up the possibility of relaxing the optimum thickness, he added.

This technology is targeted at both memory and high-performance logic applications, making CMOS an important goal. Therefore, in addition to the n-channel transistors currently demonstrated, p-channel transistors and CMOS are under development. Potential issues such as implanting the solid-source diffusion layers, though a well understood procedure for forming source and drain extensions, are being studied. And possible designs for mimicking long gate length devices using a series connection of transistors are being investigated. Although these are important issues, they can potentially be resolved through design and engineering optimization. The encouraging initial results, and the fact that the process is based on established manufacturing materials, tools and techniques, are new blood for an old technology.