CMOS: A Hard Act to Follow

		At a Glance
	What's ahead in the new millenium? When I asked CTOs, heads of R&D and VPs from the top fabs, most predicted CMOS processing will endure for the next 10 to 20 years. Here they discuss how this will occur and what strategies are in the works to maintain their competitive edge. Some responses were unexpected, though not entirely surprising.

People Want More Interaction With The World of Data

Russ Lange, IBM Fellow, director of silicon technology strategy, IBM

Moore's law has been a useful guidepost for technology development. But in the much more complicated world we're entering, it's usefulness may be diminishing because it doesn't predict future value, the thing that determines what we ultimately develop. If you look at the extrapolated average growth rate of semiconductor products and where it intersects the extrapolated gross world product, by 2042, everything will be made of silicon. That leads me to question just how much computing does the world really need? Would you like 100X more computing capability? With systems veering off into different directions, what makes a system important to people is changing. And silicon technology has to both anticipate those kinds of changes and respond to them. That's where the new value comes in. We've got to be thinking about which technologies are suitable for the emerging world of broadband information technology. For example, our involvement in technologies like silicon germanium, which allows users to interact with the network at high speeds, becomes more important than enhancing microprocessor frequency. The bottom line is, people pay for what they think they really need. And today that seems to be increased interaction with the world of data out there.

No Matter What the Technology, The Bottom Line is Cost
Dr. Ludo Deferm, vice president of business development, IMEC
Is there something beyond 50 or 30 nm? It's already proven we can make small MOS devices, but it doesn't mean the integration of these devices results in a manufacturable technology. Small transistors are prone to statistical variations. However, the impact of these variations on the circuit performance and reliability has still to be investigated. For gate oxides with a thickness ~ 1.5 nm or smaller, the tunneling current through the gate becomes very important, possibly resulting in unacceptable power consumption in circuits. So we'll likely need to find a replacement for SiO2 beyond 70 nm geometries. There are many new materials being investigated that can be made thicker with the right electrical performance, but all have disadvantages, like thermal incompatibility and interface problems with Si. To overcome this, the gate electrodes may be placed after the junctions, and metal can be used instead of polysilicon. There are also quantum effects and mobility degradation issues to address. But I'm certain it won't stop CMOS from being used because I don't know of any other device with the same kind of properties. Performance alone is no longer driving new technologies -- price has become a much bigger issue than in the past. So scaling technologies down, implementing more metal layers and making full systems on chips must in the final analysis be cost worthy.

Manufacturing Solutions Face Huge Invesments
Mike Splinter, senior vice president, worldwide manufacturing, Intel
In the fab there are a couple of inflection points coming up. One is 300 mm, a big transition not only for Intel but for the industry. It's a huge investment on the scale of $2.5B per fab, and its going to make boundaries more prevalent in the industry. Because of the size of the wafer we'll go to the next level of automation, moving product from machine to machine. Two things associated with 300 mm are the ability to invest in an economically sized factory and the product volume necessary to fill it. With the small number of companies that will meet the requirements, it creates a greater shift in the already changing industry landscape from vertically integrated semiconductor companies to companies just doing product design and then farming out production to wafer and assembly foundries. A second inflection is on the supply line. This is an Internet society, so the customers want their orders right away. From customer to sales to the planning group and on to the factory and the supplier, we've set in motion programs where we are doing all those steps and communicating to all the groups instantaneously. To stay ahead of the game, we're taking on more responsibility for our future by investing with our suppliers and developing the technologies we'll need.

Communications: New Driver of the Industry
Dr. Mark Pinto, chief technical officer, Lucent Technologies Microelectronics Group
As we enter a new century, communications is replacing computers as the driver of the semiconductor industry. Our technology strategy will revolve around providing communications systems in silicon, supported by a comprehensive CMOS-based modular processing platform. We augment our basic CMOS process with mix-and-match modules where needed to provide enabling capabilities, such as BiCMOS or flash memory. We're also incorporating software and systems expertise directly in our systems-on-a-chip (SOC) technology. To meet the breadth of today's applications, we've made acquisitions to complement a century of Lucent's communications expertise. For example, we acquired a company that develops software for GSM cellular phones so we could incorporate this technology into our GSM chips. Design work that traditionally has been done by systems houses is migrating from the board level to the chip level. Engineers from a company we acquired earlier this year are applying SONET system designs into our networking ICs. This frees makers of network access and transport gear to apply their engineering talent toward developing higher-level customer service features. I think the coming decades will see even more industry movement away from general silicon providers toward total systems solution providers.

Challenges, Yes, But Not Insurmountable
Dr. James Prendergast, vice president and director; physical science research labs, Motorola Labs
In the next 20 years, I see CMOS alive and well but with a few changes. I think optical lithography at 157 nm will happen, although 126 nm is very questionable, and other lithography solutions such as EUV, SCALPEL or multi-E-beam will likely assume the baton. SiO2 gate dielectrics will be replaced with very high permittivity dielectric, the polysilicon gates with metal gates and bulk silicon substrates with thin-film SOI substrates. I'm also optimistic about numerous engineering challenges such as source-drain tailoring, multi-threshold circuits and dynamic threshold devices being overcome. Exotic packaging solutions like die-on-die solutions and free space optical interconnects will become common. Nevertheless, CMOS processing will still be following a traditional 'top-down' approach. Beyond the 20-year horizon, an alternative approach is emerging in which individual molecules, nanoscale in size and uniform in nature, are used to fabricate device and circuit components. The organic and inorganic molecules can be synthesized with unique chemical, physical and biological properties that could be used to promote self-assembly to one another and to specific surfaces resulting in logic and memory functions. Molecular electronics is a 'bottom-up' approach of building what you need rather than eliminating what you don't. It has the potential of reaching sub-10 nm dimensions and may impact mainstream products decades from now.

Technology to Break Down Barriers
Dr. Kunihiko Niwa, general manager, Engineering Planning and Coordination Division, NEC Corp.
Humans are the most curious of animals, forever trying to learn more about the world around them. In thousands of years of evolution and looking forward to the future of technology in the new millennium, our curiosity will move us to further change, breaking down barriers in the world around us. Just look at the Internet. This has spurred NEC's tremendous effort into the development of interface technologies and systems that will enable people to use information technology as unobtrusively as we use a watch to tell the time. We see speech recognition, visual recognition, voice synthesis and interpretation systems already making a difference in how we can interface with technology and make it work for us rather than have us work for the machine, as we do today. Making advanced capabilities to give computing systems invisibility to the user takes the creative and complementary development of software, systems and hardware IP. At the core of it all will be semiconductor devices that encapsulate all these functions in a single device. Current CMOS technology can provide virtually a whole computer system on a single chip, but there is still more room for expansion, we believe down to the 5 nm level. That will enable devices incorporating vast capabilities in a portable and less obtrusive form so that IT will continue to have a great impact on the quality of our lives.

Systems Will Drive Future Technologies
Dr. Rajeeva Lahri, senior vice president, deputy chief technology officer, Phillips Semiconductor
We're moving from a chip era to a system on silicon era. Memory and logic will still be there, but with the capabilities process technology offers us, we'll be able to put more and more functions on a chip, like embedded flash memory, DRAM and RF functionality. The 0.18 µm technology has the capability to put almost 10 million gates, 40 million transistors, on a 1 cm2 chip. With gate densities doubling every 2-3 years, this puts enormous capabilities at the hands of designers and hence the potential to put a lot of mixed functions on a single chip. Every time you take a signal from chip to board and back, to another chip, you consume a lot more power, lose signal integrity and add delays. Additionally, there's a small form factor issue that will drive single-chip solutions. At 50 nm, we're looking at the possibility of more than 100 million gates on a chip, and here I think interconnects will become an even greater factor. Device and interconnect parasitics will become increasingly significant in determining overall chip performance. This will drive novel device architectures like 3-D integration, silicon-on-anything (SOA) and interconnect architectures like optical interconnects. While CMOS will continue to be a mainstream technology, 100 million gates puts a lot of raw power in your hands, and use of mixed technologies (embedded flash, RF, BiCMOS) will increase. All caches and second-level caches and flash memory will be part of the system itself. Systems will be the driver of future technologies.

SOC, Yes, But the Real Competitive Edge Will Be IP
Mike Thompson , operations manager, Crolles Facility, STMicrolectronics
As with many others, we see a trend toward the integration of more functionality onto chips or SOC. The advantage will go to companies that are broad-based and active in virtually all areas from CMOS logic to analog and mixed-signal technologies. For example, copper metalization has become somewhat of an issue in mainstream CMOS, but it's actually been around a bit longer in RF applications for making passive components. Here, ST's involvement in these areas allows for cross-pollination of technologies, making SOC a natural extension. Another big change in the industry is the consolidation amongst the equipment suppliers. So there are many fewer competitors now. This means it's becoming more and more difficult for device manufacturers to differentiate themselves by their technology. Because at the end of the day, we all finish up using the same tools from the same suppliers and doing pretty much the same thing with it. The added value is really in manufacturing functions that other people don't have, and that is found in intellectual property (IP). This means, even during lean times, we reinvest ~17% back into R&D. In the next decade, to maintain a competitive edge, IP as a commodity will have even greater importance.

Technology Is Years Ahead of Applications
Dr. Shang-Yi Chiang, vice president of research and development, TSMC
Right now, we keep shrinking geometries; whether it's 2, 3 or 4 years/generation, it doesn't matter. Assuming the pace will begin to slow down as we get close to the limit, in about 10 to 20 years from now, eventually we'll hit the limit. Suppose that happens. What's after that? It will take another 10 to 20 years to catch up to the technology, developing new products and applications. In the meantime, as the industry continues with the current CMOS device structure and nears fundamental physical limits, structure modification will push the technology one or two generations further. For example, short channel effects come into play as channel lengths shrink, creating cross talk between the source and drain. But if you use an SOI layer as the gate dielectric with a gate on top and another on the substrate, the short channel effect can be improved. And still using silicon as a framework, you can use other materials such as ferroelectrics to make small memory cells or grow GaAs on silicon to make lasers integrating silicon logic with GaAs electro-optic properties. Other technologies such as MEMS also can be integrated with silicon. We still have a long way to go before we fully utilize current technologies.

It's Now Time for The Circuits and Systems Sectors
Dr. Yoshio Nishi, senior vice president and director of research and development for the Semiconductor Group, Texas Instruments
If CMOS finally comes to the point where there is no realistic way to move forward, what will be the possible alternatives? Technologies like quantum effect devices have several fundamental difficulties today such as on/off ratio, noise margins and lack of current drive capability. And though there are many researchers working on these issues, when it comes to mainstream applications they still need to compete with and exceed silicon-based CMOS in terms of not only performance, but also cost and manufacturability. That will be a challenge. Indeed, quantum effect devices have only been successful in the commercial domain where silicon could not do the job, like emitting light, and that will remain the case. Many variations of quantum effect devices such as resonant tunneling devices, quantum dots, wires, single electron memories, even including carbon nanotubes, remain very remote possibilities. With the tremendous integration capabilities of CMOS, even though geometry shrinks may slow down in the future, there is still a lot of room to allow systems and circuits people to play the game differently. For example, they could introduce more parallelism in signal processing with novel architectures. This could enhance overall productivity, and therefore the cost per function would be improved. Today, system architecture and circuit design rely largely on silicon technology capability, with almost the same circuitry being used for many years. So, until someone invents a technology to replace silicon as an active device with adequate solution for interconnect, system architects and circuit designers will have to take the lead.

Share Risk Through Strategic Alliances
Dr. Shozo Saito, technology executive, Toshiba
As the semiconductor industry faces rising costs and shrinking design rules that are approaching critical limits, device manufacturers are faced with both technical and strategic challenges. Looking 10 years ahead, Toshiba plans to scale to under 0.10 µm geometries based on CMOS technologies. This means 4Gb to 16Gb density memories. But in addition to technology advances, to stay competitive, capacity expansion also is required. To do this, Toshiba has established strategic alliances that enable the company to increase production capacity while managing both the required investment and risk. For example, a long-term program has been established called Scalable by Design that uses a modular design approach to enable easier and more predictable transitions to the next process generation or memory density. One result has been the establishment of an alliance with Winbond in Taiwan to provide process technology in exchange for dedicated capacity. And Toshiba plans to establish a joint venture with SanDisk Corporation to increase NAND Flash production at Dominion Semiconductor. In the next decade, the industry will have to rely more heavily on strategic manufacturing alliances to meet both technical and economic goals.

Five decades ago, who would have guessed the transistor's impact on the world? Today's devices have attained a level of sophistication that far exceeds the foresight of their inventors. And today, though faced with physical limitations, the integration  capabilities of CMOS remain unsurpassed. With no clear way to evaluate the viability of alternative technologies, what is certain is that CMOS will be a hard act to follow.