Spin Processing for Frontside Applications

		At a Glance
	Wet etching technology gets a new lease on life in sub-micron frontside processes as demonstrated in the SEA 'EFASEM' Project. Well-controlled, uniform and highly selective etching, suitable for sub micron processing, has been achieved on several processes. Low particle levels are reflected in high yields measured on product wafers. Throughput and CoO achieved now supersede that of baths and spray tools.

Spin processing has been proven effective for wafer frontside etching, especially in deep-sub-micron technology. Previously it had been considered suitable only for backside etching, for example in stress relief etching after backside grinding. Partners Infineon (Dresden, Germany), Motorola (East Kilbride, Scotland), and STMicroelectronics (Crolles, France) have co-operated in the Sem iconductor Equipment Assessment (SEA) 'EFASEM' project to assess the SEZ's 203 spin processing tool for various critical frontside processes. Criteria identified for success were very high selectivity, excellent uniformity and good repeatability.

Performance in applications where dynamic spin-process technology outperforms plasma, bath and spray etch processes was emphasized. Additionally, equipment improvements were implemented, including end-point detection for better and shorter process, and high ozone concentration cleaning with low particle counts.

The partners in 'EFASEM' chose frontside processes that benefit from the better performance of spin processing and also where other equipment types are weakest, namely:

• Etching TEOS and BPSG over Thermal Oxide.
• Polymer stripping (Post metal-etch and Poly-etch).
• Polysilicon deglaze (DHF etch).
• Cleaning with ozonated DI water.
• Polysilicon strip of test wafers (frontside and backside).

Selected individual process results are described below.

BSG/BPSG etch over thermal oxide (Infineon)

Selectivity and uniformity of etch rates were determined for BSG/BPSG layers using H₂SO₄/HF over a temperature range 40°C to 60°C. Except for the highest B and P concentrations, etch rates were not very temperature-sensitive. Typically, an etch time of 30 seconds was achieved at 60°C. Fig. 1 shows the very high selectivity to thermal oxide that can be achieved. Etch uniformity with these layers is notoriously hard to achieve, and at 30% spin processing produces the best result known. End-point detection (using Luxtron1015) was used successfully on all layers examined.

Post metal-etch side-wall polymer removal (Motorola)

Fig 1  Selectivity of etch rates between thermal oxides and BSG.

Solvent strippers on the Model 203 require a working temperature of 90°C to achieve good polymer removal efficiency. Amine solvent ACT 935 was chosen for low attack of the IL Dielectric (BPSG). Optimization of process conditions gave complete polymer removal. When ozonated DI water rinse was used, the process was both particle-neutral (Fig. 2) and better than standard solvent baths. Device parameters remained unchanged, while IC yield improved by 2% at the 90% level. Similar yield improvement was shown for stripping post poly-etch polymers using a DHF/ H₂SO₄ solution.

Polysilicon deglaze, post POCl₃ (Motorola)

Polysilicon doping is characterized by a high level of particles after POCl₃ deposition (typically 120-180 p/wafer at 0.16 µm). Since these particles are detrimental to device yield, an RCA clean typically is employed after a standard bath process to remove them. Optimizing the poly deglaze process on the Model 203 and incorporating an ozonated DI water rinse greatly simplify the process (Fig. 3). Split lot tests on production wafers showed a 14% yield increase with a very satisfactory high throughput of 48 wafers/hr.

Fig 2  Particle performance data show a striking difference between batch tools and the stand-alone spin etcher.

Equipment and process advances

During the assessment period, several significant improvements were made to the Model 203 by SEZ:

• Improved temperature control of etchant and chuck.
• End-point detection (Luxtron1015) was added and made operational on a variety of layers.
• High-concentration ozonated DI water rinse was introduced.

Despite experimental changes, equipment metrics recorded in the assessment were: Uptime >80%,MTBF>500 hrs, and MTTR 2 hours.

As indicated above, the Model 203 is superior to baths and spray tools on particle counts and device yield. Some otherwise difficult processes can be better controlled -- e.g., uniformity, especially when end-point

Fig 3  A simplified process flow was realized using the spin etcher as compared to the standard RCA wet clean.

detection is used. Cost-of-ownership (CoO) is a critical issue. STMicroelectronics demonstrated a CoO of $4.38/wafer when stripping 10 µm polysilicon (frontside and backside) from furnace buffer wafers. This is significantly cheaper than using conventional reclaim techniques.

Summary of results

The 'EFASEM' assessment has shown excellent process quality and performance, allied to good results on equipment metrics for the SEZ 203 spin processor. If a criticism can be found, it lies in the difficulty that any single wafer tool has in competing in throughput with batch methods like baths and spray tools. Thus SEZ, as a result of the assessment, has introduced the four-chamber Spin-Processor 4200, based on the Model 203 process, for high-volume, low-CoO production.

This article was written by the Semiconductor Equipment Assessment Program.