Hot Processing with Vapor Phase Cleaning

		At a Glance
	By using vapor phase cleaning (VPC) as an integrated pre-step, a well- defined interface can be prepared for subsequent processes in the cluster tool. This enables excellent quality thermal growth or CVD of dielectric layers due to the better defined surface.

Current developments in 0.18 µm technology for logic and memory applications call for very high-quality and ultra-thin dielectric layers, and in situ-doped polysilicon with superior step coverage.

Stand-alone production equipment is limited in capability for such applications, since process-integrated pre-cleaning and surface preparation have become essential. It is important to examine such integrated single-wafer processing, and compare it with batch processing on stand-alone equipment, in order to avoid potential 'roadblocks' for future technology generations.

In Europe, the Semiconductor Equipment Assessment (SEA) Program undertook a study to evaluate gate dielectrics for sub-0.25 µm logic and E²PROM gate stacks and DRAM trench structures for future technology generations. Using a Siemens facility as the equipment evaluation site, the study, codenamed 'CICDIP,' evaluated hot cluster tool equipment co-developed by ASMI and Steag-AST, the Advance 800 polygon. Partners included AMS and FhG-IIS-B.

Gate stack

The influence of VPC conditioning on gate oxide integrity was examined using MOS capacitor and transistor structures. With dielectric thickness being determined from C-V and I-V curves:

• The standard VPC has two steps: wetting with methanol/ water at 200 mbar followed by an anhydrous HF step at 50 mbar. Further process options include UV and ozone treatment to reduce carbon and increase fluorine on the surface.
• Rapid thermal oxide growth can be followed by nitridation using ammonia and nitrous or nitric oxide.
• Gate dielectrics can be sealed with in situ-doped polysilicon grown at atmospheric pressure.

Fig 1a QBD for gate oxide after standard wet cleaning.

Fig 1b QBD for gate oxide after VPC and ozone treatment.

Reference wafers received a standard wet clean and furnace oxidation or RTO in stand-alone equipment to compare quality.

Compared with standard oxides after wet clean (Fig. 1a), the charge to breakdown (Q_BD) measurements for CICDIP gate oxides grown after VPC (Fig. 1b) clearly show improved early breakdown, giving greater electrical stability of devices. Bias-temperature-stress (BTS) measurements (Fig. 2) show that PMOS transistors with high fluorine content in the gate oxide (VPC3) have about five times less threshold voltage shift than those with standard gate oxide after wet clean. This improves the lifetime of the PMOS transistors in sensitive analog CMOS circuits by up to one order of magnitude and avoids expensive circuit design measures for threshold voltage shift compensation.

Trench fill capability

Integrated VPC surface cleaning before CV polysilicon deposition allows improved contact resistance between polysilicon and bulk silicon, leading to reliable contact plug and deep trench filling processes being developed on the Advance 800.

Conclusion

Integrated processing of gate stacks with superior thin dielectric properties has been demonstrated on the ASMI Steag/AST Hot Cluster in project CICDIP.

Fig 2 BTS shift for VPC-cleaned wafers at 125°C and VG,stress=-6.0V

Characterization with bias-temperature measurements shows the advantages of fluorine concentration control, and is now being complemented by Q_BD measurements. The lifetime of PMOS analog transistors has been improved by an order of magnitude. Good trench filling of deep trenches has been demonstrated with atmospheric polysilicon.

Throughput is a critical issue for a single-wafer cluster tool. From a starting point of 6 wafers/hour for gate oxide stacks, 12 wafers/hour has now been achieved. With equipment modifications that currently are planned, 15-18 wafers/hour is expected. Results reported to date show good promise for future sub-0.18 µm logic and memory technologies, and can be attributed to the close cooperation between Siemens, ASMI and STEAG-AST, in line with the goals and objectives of this SEA project.

This article was written by the Semiconductor Equipment Assessment Program.