Triple-Damascene Process Leads to Faster, Smaller Chips
Peter Singer, Editor-in-Chief -- Semiconductor International, 10/1/1999
Researchers from NEC Corp. (Kanagawa, Japan) are proposing a new 'triple-damascene' process that enables wires with different thicknesses to be mixed in one layer, without adding extra making steps. The end result is a 25% reduction in wiring delay for critical paths, and a 5% reduction in chip size due to elimination of repeater circuitry. The process is scheduled to be presented at the International Electron Devices Meeting (IEDM), Dec. 5-8 at the Washington, D.C., Hilton and Towers.
In a pre-conference abstract provided by IEDM, the researchers describe how three types of grooves -- deep trenches for thick wires, vias and shallow trenches -- are opened simultaneously. This is achieved by patterning a SiN etch stop layer (Figure). This layer is first opened over vias and thick-wire regions. Then, when the upper wiring trench is etched, both vias and thick wires are deeply etched. The etching of thin wire trenches, however, is stopped at the SiN layer.
The researchers,
who have confirmed the validity of the concept in a 0.13 µm CMOS device, say the
triple-damascene process helps get around problems associated with long,
chip-level, semi-global interconnects. Local wiring pitch and semi-global wiring
pitch were assumed to be 0.4 µm and 0.8 µm, respectively (Table). Often, to
overcome wiring delays, some interconnect levels are fabricated with a
'double-pitch' twice as large as a standard interconnect, and/or repeater
circuits are used. By selectively thickening only long 'critical path' lines,
the triple-damascene process allows delay times for these paths to be decreased
without increasing the size of all interconnect in that level. The researchers
were able to achieve a 25% reduction in delay times in the 0.13 µm device they
fabricated. The second advantage of the process is that it reduces the amount of
repeater circuitry needed, due to increased thickness of semi-global lines. This
led to a 5% reduction in chip size.
It's Not Sandpaper!
3M has developed an alternative to the traditional pads and abrasive slurries used for chemical mechanical planarization (CMP). Called fixed abrasive technology, it's like a high-tech sandpaper (But don't call it that!) where small composites of mineral (cerium oxide) and bonding material 200 µm wide and 40 µm high are positioned on a backing. The composites are shaped precisely and provide a third dimension of mineral as well as ample space for both a lubricant and spent material.
In work presented at the recent VLSI Multilevel
Interconnect Conference (VMIC), 3M said the fixed abrasive technique had
significant advantages in CMP, including higher selectivity to wafer topography,
lack of dishing and ease of use.
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