More Results Flow From the SEA

Results are now emerging from the second phase of the Semiconductor Equipment Assessment (SEA) program for projects that began in 2000 (see Semiconductor International, October 2000). SEA's focus is on proving that innovation in emerging equipment, including 300 mm, is productive, cost-effective and compatible with state-of-the-art applications that satisfy the industry's roadmap.

While the biggest single increase in productivity still promises to come from a move to 300 mm wafers (a factor of 2.25), its momentum has yet again been retarded by economic considerations and the cyclic nature of the semiconductor industry. Instead, productivity improvements during the past five years have been driven by focus on issues such as scaling, improved yield/control, throughput, equipment utilization, and process flow time reduction — all items strategically targeted within SEA. In fact, at the outset of the SEA program, it was noted that the combined improvements possible could give a ~4.5× improvement in productivity, which is double the improvement predicted for a move from 200 to 300 mm wafers. Progress in such activities at 200 mm also migrate into 300 mm equipment quality and productivity.

SEA projects cover a full range of equipment disciplines (Table). The results presented here are from advanced lithography (ALASCA), dry etching (I-SPEEDER), automatic process control (APC 300) and improved cleaning techniques (OXEPICLE and STEAM).

Project ALASCA assessed the performance of ASML's first-generation 193 nm step-and-scan exposure tool, the PAS5500/900. The equipment, placed at IMEC, was evaluated for its performance and application to key levels in advanced CMOS technologies. The project also provided direct access to a 193 nm lithography cluster for a global consortium of project partners: AMD, Cypress, IDT, Infineon, Intel, Micron, Motorola, Philips, Selete and Texas Instruments.

The equipment was progressively upgraded during the project, providing a system specified for at least 130 nm line features. Addition of an enhanced Zeiss Starlith 950 lens and improvements in resist performance enabled evaluation down to 100 nm feature sizes. This was considered necessary because progress in 248 nm lithography has driven applicability of 193 nm lithography to 130 nm applications and beyond.

	1. Resist cross-section profiles through focus for 130 nm dense line/space printing.

Many stability parameters were monitored on a daily and weekly basis over an 18-month period, including illumination and the performance of the Lambda Physik laser (extremely stable and reliable). CD uniformity for 130 nm features in resist showed a 3 σ variation of only 6.4 nm. Figure 2 shows results after poly etch. Long-term focus was good, with a 3 σ of 68 nm for 130 nm lines, and exposure-dose control with a 3 σ of 0.23 mJ/cm². Special attention was paid to investigating possible long-term optics degradation effects but, encouragingly, none were found.

	2. This graph shows CD uniformity for 130 nm lines after poly etch. Long-term focus was good, with a 3 σ of 68 nm for 130 nm lines, and exposure-dose control with a 3 σ of 0.23 mJ/cm2.

Project I-SPEEDER evaluated an advanced deep reactive ion etch (DRIE) tool based on the Alcatel A 601E cassette-to-cassette production system for very fast, deep wafer etching. The evaluation, based at Robert Bosch GmbH, was performed on the user partners' silicon substrates (PerkinElmer and Bosch), with exposed silicon areas varying from 20 to 50%. Initially, silicon etch rates were successfully increased from the initial 5 µm/min to >8 µm/min while maintaining vertical etch profiles, a silicon etch uniformity of ±3% and selectivity to resist masks higher than 150:1 (selectivity to thermal oxide was above 450:1).

The process technology underlying this assessment is the patented Bosch process that is widely used in inductively coupled plasma (ICP) systems for the anisotropic DRIE of silicon at room temperature. A thin fluorocarbon polymer film is used for sidewall protection within sequential deposition/etch cycles.

Progressive improvements during the project included modified gas delivery, increased efficiency of ICP excitation, a new substrate polarization method, high-performance vacuum pumps, pressure regulation, substrate clamping and enhanced software.

All of these improvements were targeted at achieving a higher silicon etch rate with good silicon etch uniformity and mask erosion while maintaining high selectivity to mask materials and vertical profiles. Implementation of these upgrades provided state-of-the-art DRIE rates more than doubled to >13 µm/min without negative impact on profiles, selectivity or uniformity. New process regimes were also explored with higher gas flows, process pressures and higher rf power from the ICP power supply.

	3. Process repeatability was monitored for more than eight months. Although results show some drifts during latter runs, the behavior was subsequently solved.

Key equipment parameters were monitored on a weekly basis throughout the 16-month project, including process chamber leakage rate, pump delivery rate, zero point drift of the chamber baratron gauge and chamber pressure for constant gas flows. This monitoring program showed completely stable and repeatable results during the entire period. Assessment of both wafer handling and plasma ignition were evaluated with the system performing >10,000 handling procedures and additionally >3200 plasma ignitions without any error or alarm messages.

	4. A DRIE tool was tested under simulated production conditions by etching wafers for many hours without interrupting processing, to allow heating up.

The high anisotropic etch rates and control achieved has opened up a new and wide range of manufacturing possibilities for sensors and microsystems. Furthermore, the ability to etch stress-free at a high rate has opened up new applications in the area of wafer-level packaging (WLP).

Project APC 300 is integrating the advanced ASI Hercules plasma process monitor tool based on self-excited electron resonance spectroscopy (SEERS) with supervisory and analytic capability onto several plasma etch tool types. Participants include Infineon Technologies at its SC300 Dresden and Regensburg facilities, AMD and STMicroelectronics. IBM, International SEMATECH and Lam are also involved with the project.

At SC300, the prime evaluation site, several plasma reactors, each equipped with a Hercules plasma sensor and network, are linked to a supervisory system capable of interface with each of the plasma controllers. The setup includes tools for three different processes and includes different chamber types (both capacitive and capacitive with additional ICP chambers). The supervisory system enables 100% control over all monitored etch tools for up to 12 chambers at a time.

	5. Typical monitor plots for a four-step plasma etch process, where the characteristic shape of the four sections can each contribute to a process ‘fingerprint.’

Fingerprinting is affected by recording collision rate and electron density of each process step. This fingerprint can then be compared with that of an optimum step to determine process drift or out-of-limits operation. For example, following data compression plots showed unusually high collision rates starting on day 13 of a 40-day test period at Infineon SC300. This was traced to arcing (a common problem in dry etch), caused by polymer build-up in the chamber resulting in a high level of polymer particles in the plasma as identified by the high collision rate.

6. The first production lots after improved conditioning show the optimization of the conditioning cycle necessary to reduce particulate levels. The first 50 wafers after the cleaning procedure are shown in red. Test wafer usage could be reduced to 37 wafers if oxidized wafers were used (first production lot in blue), but by far the most effective recovery treatment (green) was achieved with five resist-coated wafers followed by five poly dummy wafers.

One of the most promising revelations of the results obtained at Infineon SC300 was the ability to correlate SEERS data with electrical test data. In particular, gate contact length bias was found to correlate very well with collision rate. This ability to foresee electrical results many days in advance has provided a powerful tool to improve yield.

Overall, the project results have provided proven examples of the benefits of APC, including fault detection, release to production, more rapid tool recovery, improved chamber conditioning and, importantly, correlation of the internal plasma parameters with IC electrical test data, which enables the identification of potential yield limitations weeks earlier than before.

Project OXEPICLE evaluates next-generation wet processing equipment from Mattson (the STT300) placed at the 300 mm pilot line of STMicroelectronics in Meylan. Partners Infineon (ICs), Wacker (virgin wafer supplier) and IMEC (research institute) ensure that a blend of expertise is available.

The activity is focused on gate stacks, low-temperature silicon epitaxy and SiGe alloy hetero-epitaxy for future technologies at 100 nm and below, where pre-clean will be a strategic issue. The project is structured to link recent advances in cleaning with recent advances in tool concepts. By combining diluted (RCA-based) and ozone chemistries, critical cleans can be performed in a single tank tool. The lower chemical consumption and footprint offer large advantages from both an ESH and economic point of view.

Of particular interest is the preparation of wafers with hydrophobic surfaces to feed a nearby hot cluster tool for either RTO growth of ultrathin (2 nm) gate oxides or low-temperature SiGe epitaxial layers. The equipment has demonstrated etch uniformity better than 2% wafer-to-wafer and batch-to-batch for HF type (IMEC) cleans in the presence of sacrificial oxide with very low DI water consumption.

	7. The principle peaks E1 and E2 in spectroscopic ellipsometry traces indicate the high quality of layers produced following cleaning and the layer control that can be implemented during deposition.

The results obtained already indicate great potential for advanced surface preparation for pre-epitaxy and pre-gate cleaning, and that the cleaning specifications of the ITRS for 100 nm geometries can be met.

Proof of concepts

Most SEA projects are carried out under "close to production conditions" on advanced beta tools. Alpha tools can also be evaluated in so-called SEA proof-of-concept (POC) tests. One such project was STEAM, with the evaluation of a novel post-CMP cleaning technique from Contrade that uses no chemicals. The equipment was placed at the research institute Fraunhofer-Silicon Technology in Germany with Infineon having been involved in a prototype version. This Vergine R concept uses super heated steam directed onto the wafer surface onto which a thin DI water film is continuously fed. The steam bubbles implode, causing non-contact energy to remove particles left by CMP processing. The wafers are cleaned on both sides vertically in the steam module and can be complemented by the in situ brush module if desired.

The partners have demonstrated superior particulate and ionic cleaning performance at low cost, and the method is environmentally friendly. It is anticipated that the concept will work well on patterned substrates. Initial trials of Vergine R on complex phase-shift masks have shown excellent results.