Trench Warfare: CMP and Shallow Trench Isolation

		At a Glance
	STI's advantages -- better dimensional control and packing density than LOCOS -- can be enjoyed once issues of pattern density management during CMP are solved. Learn how slurry and pad choice affect planarity as well as yield in single-step STI CMP processes.

Shallow trench isolation (STI) structures represent CMP's hottest new application for device-level processing. In fact, they could not be manufactured without chemical-mechanical polishing (CMP). STI increases transistor packing density, allowing more functionality and speed per unit area. While several fabs have had STI in production for some time, mainstream implementation is only now beginning to surge. To date, CMP's sensitivity to device pattern densities has been augmented from the design side using reverse mask and etch techniques or dummy structures. Without pattern density management from the design side, current CMP consumables (originally developed for oxide interlevel dielectric [ILD] planarization) will, in most cases, not meet the requirements of a single-step STI CMP process. We demonstrate recent improvements in polishing pads and ceria-based high-selectivity slurries that are driving STI CMP performance. In this critical processing area, engineers are winning battles, but the war is far from over.

STI CMP challenges

STI is the most critical CMP application, presenting several technical, economic and manufacturability challenges, especially in the area of process flow integration. The primary goal in STI CMP is leaving the post-polished device surface as planar, clean and defect-free as possible.

STI is primarily designed into a device at or below the 0.25 µm technology design node, with selective use at 0.35 µm. STI replaces the traditional LOCOS (local oxidation of silicon) structure,¹ as it offers a more controlled form of electrical isolation. LOCOS structures consume larger amounts of real estate because oxidation expands the isolation region laterally in proportion to its depth (Fig.1), becoming a critical problem at sub-0.35 µm design geometries. LOCOS yield is similar to STI until isolation spacing reaches a critical minimum level, after which it falls sharply (Fig. 1d).² LOCOS also results in a non-planar surface, creating depth of focus problems during subsequent lithographic patterning of the polysilicon layer. STI offers better trench depth and width control, and greater packing density. It uses photolithography and etch techniques to define the isolation areas, then TEOS (tetraethylorthosilicate) or HDP (high-density plasma) oxide deposition into the silicon trench.

Fig 1 The STI structure reduces lateral encroachment relative to LOCOS to increase transistor packing density. Effects on yiled (d) are most pronounced for sub=0.35 mm devices.

Following CVD deposition (Fig. 2a), the STI structure is polished (Fig. 2b), with performance measured using many of the factors shown in Fig. 2b. Successful STI integration considers: CMP process integration and planarity, particularly focusing on nitride and trench oxide erosion; CMP endpoint detection, identifying complete removal of active area oxide without excessive over-polish; and prevention of microscratching and particle defects.

Process integration

Although STI offers critical enabling technical capability over LOCOS, it also involves additional and more complex process steps. Prior to CMP of the oxide overburden, several factors can affect the success of the CMP step and the STI process, including:

• Pattern density variation across the device -- Use of dummy structures, an additional nitride cap layer or reverse mask and etch to pre-planarize the oxide over active areas can significantly reduce this variation.
• Nitride deposition thickness and non-uniformity -- Nitride protects all active areas during CMP and provides a sufficient trench oxide thickness margin without adversely affecting photolithography performance.
• Nitride etch -- Wall slope affects oxide fill characteristics.
• Trench depth -- Dictates step height and the amount of oxide removal needed prior to single-step CMP.
• Type of trench oxide -- For example, TEOS and HDP oxides possess significantly different gap fill properties, changing the 'effective' pattern density. Void formation in trenches can also reduce CMP performance.
• Trench oxide thickness -- Depositing a thicker oxide on the wafer lengthens the CMP process and enhances planarization.

  Fig 2 CMP must competely remove deposited oxide above the nitride polish stop while minimizing nitride erosion and dishing in the trench.

Significant interactions can occur between the CMP step and subsequent process steps. These include:

• Post-CMP clean -- Polishing must leave the wafer surface in an easily cleaned state without scratching the device surface. Post-CMP clean cannot correct scratch defects, and a light buffered HF (BHF) step can increase trench oxide loss and enhance scratch defects.
• Nitride strip -- Stripping the sacrificial nitride layer after CMP is significantly hampered by insufficient active-area oxide removal, potentially causing significant yield degradation.
• Pad oxide and sacrificial oxide strips can increase trench oxide loss beyond that lost during CMP.
• Poly masking and etching -- A non-planar surface, due to excessive trench oxide dishing or thickness variation during the CMP step, can cause poly masking problems and poly stringers after etching. Excessive dish ing also can cause a poly 'wrap-around' effect that degrades device performance.

Integrating the many process steps involved and understanding their effects on one another is important to achieving a successful high-yielding STI process.

Planarity

The process window for STI is smaller than ILD. But since the oxide dielectric materials are similar, standard ILD consumable sets (pads, slurries and carrier films) were adopted for STI. Successful CMP of STI features is highly pattern sensitive,³ primarily due to pattern density effects. Since it is imperative to remove all the oxide over very dense or large active areas, lower density or isolated small structures become over-polished. Over-polishing that removes the entire nitride stop layer or significantly erodes trench oxides can hurt device yield. To manage these issues, device manufacturers most commonly add complexity to the process by performing a reverse photomask and etch pre-planarizing technique.^4,5 This technique reverses the STI photomask image, exposing and subsequently etching oxide over the nitride active areas. Alternatively, manufacturers add dummy structures to the design where possible,⁶ or even use a second nitride layer on top of the oxide.

Fig 3 This specially designed layout tests CMP's management of varying pattern density.

To reduce process steps and complexity, many device manufacturers are pursuing STI CMP processes performed on aggressive pattern density designs without the photo and etch steps required for the pre-planarization, dummy structures or additional nitride layers. The STI density and pitch pattern test mask, developed by MIT (Fig. 3),⁷ features 4800 Å deep silicon trenches, 8,000 Å TEOS oxide deposited over 1960 Å of silicon nitride and 150 Å thermal oxide. Engineers use this mask to measure effects of pattern density on trench dishing and nitride erosion.

We found that while minor improvements in trench erosion, for example, can be made through process parameter adjustments, such as down-force (polishing pressure), choice of consumables (pad and slurry) makes a more substantial difference.⁸

Using a SpeedFam-IPEC Auriga CMP system, we polished the MIT wafers using three types of oxide polishing slurries, identified as 'A,' 'B' and 'C,' and two different conditioning techniques, normal and reduced. We also compared single-step and multi-step processes using slurry C. The results (Fig. 4) demonstrate nitride erosion of ~500 Å across a wide pattern density range (90% to 30%) with standard ILD polishing slurries A and B. However, the high-selectivity slurry C in multi-step mode dramatically improved nitride erosion to <100 Å across the wide pattern density range. Conditioning did not appear to be significant.

Fig 4 Using the MIT wafers, standard slurries with the IC1000B/Suva IV pad led to nitride erosion of ~500 Å with a strong dependence on pattern density.

Using the same three slurry types and pad conditioning processes, we demonstrated that trench oxide erosion (or dishing) is also quite sensitive to pattern density, and significant differences also exist between slurry types. Slurry C performed much better for trench erosion than slurries A and B (Fig. 5). Oxide erosion performance differences also exist between the ILD slurries, with slurry A outperforming slurry B, most likely due to differences in source and type of silica abrasive. Less aggressive conditioning offered a very slight improvement, far outweighed by negative process stability effects.

New high-selectivity ceria-based slurries tend to polish HDP oxides with greater stability than TEOS- based oxides. Fig. 6 compares ceria-based slurries C and D to a fixed abrasive STI pad, while also comparing nitride erosion using two different process schemes and Slurry C on a logic device. The fixed abrasive pad holds the (ceria-based) abrasive in place with a hard resin as opposed to typical free-floating slurry abrasive. The logic device contained distinct 90% and 30% pattern density areas. The data illustrated that, although all test cells had roughly the same amount of nitride removal in the 90% dense areas, a significant difference in nitride removal amount existed in the 30% dense areas. Slurry C demonstrated a dramatic improvement in nitride erosion performance when run in a multi-step polish process instead of single-step. This multi-step process did not affect slurry D or the fixed abrasive pad. In all cases, nitride erosion with the experimental consumables outperformed results using low nitride selectivity polishing slurries A and B.

Fig 5 Using MIT wafers and the same slurries and pad in FIG. 4, trench dishing is sensitive to pattern density and slurry type, more so than single-versus multi-step processing.

Fig. 7 compares the same experimental STI polishing pads and slurries for trench erosion performance. Slurries C and D exhibited significant trench erosion, but still would likely have less trench erosion than standard oxide polishing slurries. The fixed abrasive pad demonstrated excellent trench erosion results and continued to perform well with increasing over-polish, contrary to traditional slurry over-polish results.

Endpoint detection

Ensuring all oxide is removed from the nitride active area and simultaneously controlling the amount of over-polish during the STI polish process is often the difference between high yield and scrap. Residual oxide makes removal of the sacrificial nitride layer extremely difficult, thus neutralizing the active area. Conversely, over-polishing leads to excessive nitride erosion and trench oxide loss that can destroy device yield. Therefore, the ability to stop the polish process at a particular point is critical. Though STI process windows are typically quite narrow, some advanced consumables can widen the window by minimizing nitride erosion and trench oxide loss upon over-polish.

Generally, if oxide to nitride selectivity is greater than 15:1, monitoring wafer carrier motor current provides good endpoint detection. We monitored carrier motor current when polishing with slurry C. During HDP oxide polishing, the carrier current is in a normal range, but as the oxide steps planarize, motor current increases. As the nitride active area becomes exposed, carrier motor current falls rapidly. The endpoint detection system recognizes this characteristic downward slope and signals endpoint. Polishing is stopped several seconds later to ensure complete oxide removal.

Fig 6 Removal rate at 30% pattern density depends on slurry type and process type.

In cases where oxide to nitride selectivity is low (<15:1), monitoring carrier motor current is ineffective because the frictional force delta between oxide and nitride film layers is small. Optical endpointing provides a suitable alternative, although optical techniques are also effective with high-selectivity slurries since they are insensitive to frictional loading. Optical endpointing directs a broad band light source onto the wafer surface as it is being polished, receives a return signal, and develops and analyzes a waveform to produce a number. The number decreases during wafer polishing, signaling endpoint when the number reaches or falls below a pre-programmed nitride target thickness. We polished the MIT wafers, detected the endpoint and over-polished 100 Å of nitride.

Defects and microscratching

Defectivity and cleaning are critical with STI CMP processes. Since it is a device-level process, contamination and defectivity issues are more important than at upper ILD levels. Microscratching is a common problem with STI, and it is not always obvious immediately after the polishing process. Once the oxide has been cleared over the nitride active areas, an interface between the oxide field areas and the nitride active areas develops, creating a frictional and planarity boundary (due to dishing). The boundary often traps larger slurry or other particles and, if released, can skip across the nitride active area surface. Even if the skipping particle does not create a visible defect in the silicon nitride layer, it often creates stress points in the underlying pad oxide and silicon surfaces, which become visible after the nitride is wet etched. The defects appear as small chatter marks⁹ and can damage active silicon regions.

Fig 7 The fixed abrasive pad offers minimal trench dishing relative to high-selectivity slurries C and D, though levels are still lower than those expected for standard slurries.

The source of the suspect particles is often slurry particles or slurry mishandling. Slurry particles can come from agglomerates in the dispersion, dried slurry falling into the mix, foreign contaminants, unclean slurry lines or a poorly cleaned CMP tool. Proper slurry handling and tool maintenance techniques can minimize such effects, as can point-of-use slurry filtration. A point-of-use filter (pore size rated as low as 0.3 µm) improves microscratching performance, while filters of larger pore size can be run in the slurry distribution loop to lengthen the life of microfilters.

Particulate defect performance is often a complementary blend between the polishing process, consumables and the post-CMP clean process. Typical low selectivity oxide polishing slurries and processes for STI can utilize the same post-CMP cleaning techniques as ILD processes. Cleaning performance of oxide polishing using an Auriga C dry in/dry out polishing system and Slurry A is shown in Fig. 8.

Alternate STI slurries, such as those with ceria-based abrasives, also seem to clean well with standard oxide slurry cleaning processes. We cleaned oxide wafers, dipping the wafers in slurry C and cleaning on a brush scrubber using a standard NH₄OH and DI water process (Fig. 9). The results are similar to those a slurry A dip would provide. At the moment, all advanced STI consumables, including the fixed abrasive pad, showed that defects due to scratching are still an issue, despite significant recent improvements.

Fig 8 Defect levels following dry-in/dry-out polishing using traditional ILD slurry A are actually lower than the pre-clean levels. (note: Tencor 6420 inspetion tool used)

Conclusions

STI and CMP technologies go hand-in-hand and are here to stay for foreseeable IC device generations. But, the industry needs to make many technical and cost improvements as STI production implementation continues. Without pattern density management from the design side, the industry needs STI-specific consumables for single-step STI CMP. Improving STI-related CMP polishing and cleaning equipment is important, but improving the performance capability of polishing pads and slurries is driving overall STI CMP performance.

Acknowledgements

The author gratefully acknowledges Frank Krupa for technical discussions and editing; Kathy Leaf, Paul Holzapfel, Inki Kim, Nancy Lund, Sanjay Basak and Sherry Zhu for their contributions.

References

Fig 9 Defect levels following slurry C dip and NH4OH/DI brush cleaning.

1. M. Weling, Solid State Technology Seminar, Mar. 1997.
2. Fu-Liang Yang, et al., VMIC Conf., IMIC-108, June 1998, p. 496.
3. J.T. Pan, et al. VMIC Conf., IMIC-108, June 1998, p. 472.
4. B. Dovari, et al., IEDM Technical Digest, 1989, p. 61.
5. J. Boyd and J.P. Ellul, J. Electrochemical Soc., Vol. 143, No. 11, Nov. 1996, p. 3718.
6. B. Stine, et al, CMIC Conf., June 1996, p. 421.
7. Massachusetts Institute of Technology.
8. S. Hosali and D. Evans, et al., CMP-MIC Conf., ISMIC-200P, Feb. 1997, p. 52.
9. C. Dennison, CMP Users Group, Dec. 1998.

 

Jim Schlueter manages the STI CMP process development effort at SpeedFam-IPEC Inc., and earlier was a process development director for SpeedFam Corp. Prior to SpeedFam, Jim was a member of the technical staff of SEMATECH, where he performed a variety of roles in PVD and CMP project management. Formerly he was a process engineer at Eaton Corp. and at Sperry Corp. He holds two bachelor of science degrees from South Dakota State. Phone: 408-705-2624 Fax: 408-705-2786 email: jschlueter@sfamipec.com