Masks: What's Behind Rising Costs?

		At a Glance
	Next-generation lithography methods require complex masks. Whether advanced optical, EUV or SCALPEL, each poses challenges that effectively up development and manufacturing requirements. For advanced optical OPC and phase shift masks, multiple masks requiring longer write times increase production costs; EUV reflective masks pose challenges because of the unfamiliarity of the technology; and SCALPEL masks face small, 100 nm, membrane dimensions. But despite the potential roadblocks, progress continues in all arenas. The mask CoO numbers from the various technologies are high, but surprisingly close. This article looks at the complexities that are driving the cost of reticles.

Twenty years ago, lithography systems were based on 1X scanners, and photomask costs comprised 4% to 5% of total revenues. Today, the numbers look better. For every $100 of semiconductor revenue, fabs are spending $1. 50 on masks -- 1. 5%. In contrast, semiconductor equipment may consume 15% to 20% of total revenue. While there is a tendency to focus only on leading-edge technologies at critical levels, in a set of 25 to 35 masks there may be only 1 to 6 aggressive optical proximity correction (OPC) and phase shift masks (PSM) depending on the design. What is creating industry concern is the cost of a single mask for critical levels. At the 100 nm node, a PSM could be $50,000, an EUV mask $40,000 to $59,000, and a SCALPEL $27,000, compared to $5,000 to $10,000 for a standard binary mask. As device geometries shrink, Dr. Klaus Rinnen of Data Quest sees an increase in the total number of layers requiring advanced lithography, thus further increasing mask costs. Knowing potential hot spots in advanced optical, EUV and SCALPEL mask technologies can ease the transition.

Key issues

In mask making, cost is dominated by the cost of the writing tool. Longer write times mean higher costs. Technologies that require two or more writes, smaller dimensions or increased complexity add to write times. Meeting specifications for CDs, registration and defect targets can impact yield and further increase cost. While phase error and repair of PSMs will one day attach other cost elements, these capabilities ultimately will serve to reduce manufacturing expenses. For unlike device processing, it is cost effective to repair a lithography mask because it consists of only one layer. In an effort to avert rewrite cost, there is considerable interest in repair technologies. The repair of quartz damage has been particularly elusive. But engineers at RAVE LLC (San Jose, Calif. ) have demonstrated the ability to repair quartz, chromium and molybdenum silicide in a lab environment -- the result of a SEMATECH contract. Defects are identified with data maps provided by defect detection tools from suppliers such as Applied Materials and KLA/Tencor, and targeted regions are nano-machined at a rate of 2-3 hrs/mask, according to RAVE president Barry Hopkins. Cost of the repair system is expected to be $3.5M to $4M, comparable to advanced focused ion beam and laser ablation tools. A tool is targeted for customer testing by the end of the year.

For advanced lithography masks, electron-beam write tools provide better resolution. But for production, laser tools provide the best cost of ownership (CoO) because as many as 32 beams can write in parallel. This typically means write times 3-4X faster than with e-beam. To combine laser speed with e-beam precision, Etec's (Hayward, Calif. ) strategy is to increase pixel delivery rates as feature geometries decrease. Their goal is to keep write times at 4-6 hrs/mask, a factor of 2 better than current e-beam rates.

Time is money, and the sheer cost of mask technology is creating a trend to cost sharing. DuPont Photomasks' Reticle Technology Center (RTC), for example, brings under one roof photomask engineers and semiconductor engineers who then work with the strategic equipment and materials suppliers. The real value of technology and cost sharing is speed, shortening development cycles. According to Ken Rygler, executive vice president of marketing and planning at DuPont Photomasks, Inc. (DPI), it once took six months to characterize a new mask photoresist. Now it can be done in six weeks at the RTC. DPI's principal focus at the RTC is on extending the life of optical lithography through leading-edge binary masks, PSM and OPC.

For next-generation lithography (NGL), the Mask Center of Competency, led by Photronics (Jupiter, Fla.), will work with the industry to develop and commercialize the membrane mask technologies.

Optical mask enhancements

The 200 mm diameter EUV mask shown contains a pattern of a leading-edge Motorola microprocessor design. (Source: Motorola)

Optical mask enhancements come into play as device features dip below the wavelength of exposure light, the sub-wavelength region, because of inherent diffraction effects that blur feature edges. The most common enhancement techniques are OPC, which implements localized feature biasing sub-resolution features such as serifs and scattering bars; alternating PSMs (also known as strong shifters or Levenson/Shibuya masks); and embedded PSMs (also known as halftone shifters or attenuated shifters). PSMs reduce (with embedded) or eliminate (with alternating) the zero order mode of impinging light using adjacent structures 1807 out of phase. The 0NewsPi>7 and 1807 transmitted light destructively interfere at the feature edges, tending to sharpen the aerial image by suppressing the zero order diffraction mode and enhancing the higher order modes. The effect is to increase the spatial bandwidth of the printing process. To process the photomask, both PSM techniques require dry etching. Embedded masks etch the attenuating materials, such as molysilicide and chromium nitride, and alternating PSMs etch the quartz substrate with the etch depth corresponding to the amount of phase shift required.

The biggest topic of contention in the world of optics is the mask error factor (MEF, the transfer of CD errors from the reticle to wafer), particularly with binary and attenuated phase shift masks, according to Gil Shelden, technology champion for optical lithography. This means better CD control is needed at the mask level -- at the 100 nm node, 7 nm across the entire wafer, a third of where we are today. Currently, there is no known way to do this. So who carries the responsibility of CD control? Some say the writer has a bigger contribution than the blank and process; others will say the blank and process more than writer. Though faced with formidable issues, the bottom line is that embedded PSMs can reduce contact hole size by 15% to 20%, and alternating PSMs can improve resolution by a factor of 2, Shelden said. Mask CD control can be relaxed by a factor of 2 with a strong phase shifter, like an alternating PSM. This, however, comes at a price.

Alternating PSMs

Among the optical enhancement techniques, alternating PSMs produce the smallest features for a given exposure wavelength. Researchers at MIT, for example, used a chromeless phase edge coupled with a nitride-spacer process to print 25 nm features with 248 nm illumination. However, mask processing must be precise, there are design constraints, and the finished product is very sensitive to lens aberrations. In processing an alternating PSM, a grid of phase-shifted structures is created across the entire mask. Areas that contain unwanted phase changes may print as a line. Techniques such as trim masks adopted by Numerical Technologies, and conjugate twin shifters developed by Oki and adopted by IBM, remove these areas. Conjugate twin shifters are immediately attractive because they require a single mask. Two etch steps create 907 and 270° (totaling 180°) phase changes, effectively producing a softer edge that is less likely to print. For certain features, this technique suffers from aerial image intensity imbalance between the alternating apertures. Other approaches use a gradual phase change by making 60°, 120° and 180° increments; but due to aberrations, the induced phase errors can create image placement problems at the termination point near critical features.

The trim masks are meeting 100 nm design rules for Motorola's PowerPC chip with 248 nm lithography. Implementing dark field, alternating phase shifters, this technique requires two masks, one binary and one PSM, thus separating phase-shifted from non-shifted features. The upshot is two writes and tight registration, mask design limited to a Manhattan layout, and double exposures during device fabrication. However, trim masks provide the most cost-effective approach among alternating PSM technologies, according to Shelden.

Fig 1. LineSweeper reticles evaluate OPC for a particular process and exposure tool and provide appropriate rule selection for application to product reticles. (Source: ASML Mask Tools)

A two-mask approach that eliminates registration issues while implement alternating PSM technology is Canon's IDEAL. One mask is a binary and the other a simple alternating PSM consisting of equal lines and spaces, 180° out of phase. The PSM, high-contrast pattern is exposed at less than half the normal dosage. A low-contrast flood exposure of the binary reticle, containing a 4X image of the actual design, follows. Upon development, high-resolution printing is achieved where the combination of the low- and high-contrast patterns exceeds the resist's exposure threshold. A 20 nm misalignment to the left or right of the PSM line produces a small CD change, less than 5 nm, according to Phil Ware, assistant general manager/director at Canon (Santa Clara, Calif. ). The width of the PSM lines and spaces corresponds to a k1 of 0. 3 (k1 is a measure of printing difficulty; k1 = W x NA/l). This means that 125 nm geometries can be printed with a 248 nm stepper and an NA of 0. 6 when IDEAL is implemented (Fig. XX). Ware anticipates the simple PSM and binary masks will be priced comparably.

More optical enhancements

Less developed than alternating PSMs, embedded PSM technology ultimately may be more versatile because phase shifts are applied only at designated features. Though two trips through the writing tool are still required, these masks are not constrained in terms of design and show more tolerance to phase errors, according to John S. Petersen of Petersen Advanced Lithography (Austin, Tex. ). Embedded masks currently are used at the contact level, but they are gaining acceptance as a general-purpose solution. Of particular interest are high-transmission embedded masks. Because of potential manufacturablility, high-transmission masks are increasingly popular in the Pacific Rim -- for example, at Japan's Dai Nippon Printing (DNP), Korea's Samsung and Taiwan's Taiwan Semiconductor Manufacturing Co. (TSMC). For numerical apertures of 0. 5 to 0. 63, Petersen advocates the use of 18% to 20% transmittance masks for contacts and 30% to 42% for line-space features at 130 nm minimum widths. Smaller linewidths show further enhancement with even higher transmissions. Work continues to identify high-transmission materials and optimize processing.

100 nm Mask CoO Summary
	193 L/S AltPSM	193 Contact EmPSM	157 L/S Binary	157 Contact EmPSM	SCALPEL			EUV
Yielded material	$2.6K	$4.4K	$3.8K	$12.7K	$2.2K			$16.7K
Cum. yield	50.2%	49.3%	45.7%	42.9%	57%			55%
Factory cost	$315M	$269M	$240M	$320M	$187M			$216M
Mfg. Cost	$22.5K	$20.6K	$17.8K	$31.7K	$13.6K			$29.8K
Cost to customer	$43K	$41K	$36K	$63K	$27K			$60K
L/S indicates masks for critical isolated and dense lines and spaces; contact indicates masks for contacts and vias.
Source: SEMATECH

Many of the optical extension technologies are complementary, however, they cannot be arbitrarily combined. For example, off axis illumination, an accepted and widely used stepper feature, and alternating phase shift technology, do not add up to something better since alternating eliminates the zero diffraction order and off-axis keeps the zero order and throws out one set of higher orders. However, off axis illumination, high NA and scattering bars are all complimentary and when combined, increase process latitude, notes Roger Caldwell, vice president and chief operating officer at ASML MaskTools, Inc. (Santa Clara, Calif. ). High NA lens allows smaller and denser features to be printed; scattering bars allow isolated lines to also be imaged from the high NA part of the lens; and off-axis illumination selectively distributes light to that same part of the lens. With optical enhancement based on binary chrome masks, Mask Tools' approach requires just one pass through the writing tools and one through inspection adding to its cost effectiveness. According to Caldwell, binary chrome mask technology can print 130 nm features with 248 nm technology, 0. 7 NA and off axis illumination. He anticipates its extendibility to 193 nm exposure tools with potential resolutions down to 100 nm and below if attenuated masks are used.

NGL masks

According to SEMATECH, all next-generation lithography (NGL) technologies have claimed the potential to meet the sub-130 nm nodes by 2003 to 2005. Assumed is the availability of adequate resources and support provided in a timely manner. The insertion point for SCALPEL and EUV is targeted for the 70 nm node. Though the technologies are expected to require new and expensive mask processing tools, at the 100 nm node, mask manufacturing costs of SCALPEL masks may be lower than those of 193 nm and 157 nm PSMs.

Fig. 2 Using IDEAL's 2-mask process on a 248 nm stepper with 0.6 NA, 130 nm gate patterns were achieved. With 193 nm exposures, features to 80 nm are possible. (Source: Canon)

EUV reflective masks

From a mask maker's point of view, 'the Extreme UV mask is different in terms of anything previously seen,' said Jack Moneta, senior vice president of strategic planning at Photronics (Allen, Tex. ). They are reflective rather than transmissive, 4X reduction reticles. According to the SEMATECH study, overall mask yields of this relatively new technology will be comparable to SCALPEL at 55%, and better than 193 nm and 157 nm advanced optical phase shift masks. The mask blank, however, poses a problem. To reflect the 13. 4 nm EUV wavelength, the silicon wafer mask blank is coated with 80 alternating quarter wavelength layers of molybdenum and silicon. The multi-layer stack has demonstrated defect levels of ~10^-14 defects/cm², 2 orders of magnitude above target levels. The impact is an assumed mask blank yield of 29% using the SEMATECH CoO model. Currently there is no known method to repair defects added during multilayer deposition; however, past performance indicates we can reduce the mask defect density by an order of magnitude/year, according to Chuck Gwyn, EUV technology champion from Intel. 'With the present level of defect reduction, we believe a mask blank yield of greater than 60% can be achieved in the near future; our target yield is 70 to 80%,' Gwyn said. These numbers, combined with the use of visible light inspection instead of at-wavelength, can result in at least a factor of two decrease in the mask cost, he added. Once the critical reflective coating is in place, mask patterning is performed using conventional silicon processing technology, including absorber patterning using e-beam writing.

To protect the reticle, traditional pellicle membranes are not appropriate for EVU masks because they absorb more than 75% of the lithographic radiation. However, a solution may exist using a Klebanoff-Rader thermophoretic strategy where the mask is enclosed in a He or Ar environment and heated to a temperature slightly higher than that of the surrounding area. Particles are efficiently repelled from the mask with no additional absorption of EUV radiation.

The newest of the NGL technologies, EUV has demonstrated full-field patterning of a 200 mm diameter mask with a pattern for one level of a Motorola microprocessor. The mask was patterned by a team from Motorola's Advanced Product Research and Development Laboratory that works closely with researchers at Intel and AMD on EUV mask development (Fig. x).

Fig. 3 Embedded phase shift masks are commonly used at the contact level but are gaining popularity as a general-purpose solution. (Source: DuPont Photomask)

SCALPEL membrane masks

Scattering with Angular Limitation Projection Electron beam Lithography (SCALPEL) is a 4X charged particle system. The mask consists of thin, 100 nm Si₃N₄ membranes, supported by struts 725 µm thick. The pattern layer is comprised of 24 nm of tungsten to produce the imaging contrast by way of electron scattering (the electrons are not absorbed in the mask). During the mask blank fabrication process, a waffle-like pattern emerges upon etching into the silicon substrate, forming the silicon struts and defining the membrane regions where imaging occurs. The membrane regions are stitched together during image transfer to the wafer. The sturdy silicon struts serve to minimize mask image distortion. According to technology champion Lloyd Harriott, head of advanced lithography research and SCALPEL program manager from Bell Labs-Lucent Technologies, what gives SCALPEL mask technology the lowest mask CoO evaluation is its similarity to conventional binary photomasks (no OPC or phase shifting required), simple mask blank structure and utilization of standard mask tool sets.

Possible areas affecting CoO are lack of a pellicle, heating and handling concerns arising from the thin membrane. However, initial handling experience has been encouraging. At Photronics, where more than 100 SCALPEL masks have been produced, little breakage has occurred, according to Moneta. It's more a matter of learning than inherent structural problems. Mechanical and thermal modeling results also have shown promise. In modeling performed at the University of Wisconsin at Madison in collaboration with Lucent Technologies (Murray Hill, N. J. ), stresses in the resist, bilayer and membrane were shown to influence the change in in-plane distortions of the mask membrane due to mounting in the e-beam writer, pattern transfer, and mounting in the exposure tool. The resist was determined to be most influential, the membrane the least. Modeling the effect of mask heating during step-and-scan indicated that the maximum temperatures of the heated cells were insensitive to the thermal conductivity of the membrane and that transient distortions that occur during the exposure process can be controlled by adjusting the duty cycle pulse width and profile.

Fig.4 The cross-section of a SCALPEL mask reveals membranes, 100 nm thick, supported by silicon struts. (Source: Lucent Technologies)

New directions

ASICs are going to be the technology driver of the future, according to Mask Tools' Caldwell. For years, memory devices were the technology drivers, and as interconnect layers dominated the cost of the chip, microprocessors drove technology. Now with mask costs becoming a growing factor in the total product cost, the number of wafers/mask becomes a major part of the CoO equation. Unlike memory chips that use tens of thousands of wafers/mask, and microprocessors, which use thousands of wafers/mask, ASICs, on average, run just 250 wafers. With mask sets approaching $250,000, this could mean $1,000 added to the cost of producing one wafer, compared to l$25 for DRAM. The ASIC and system on a chip (SOC) industry must find a solution to the high mask costs. Some Japanese companies will use e-beam direct-write on several layers to avoid making a mask; this is practical at l10 wafers/mask. Some Taiwanese foundries are offering to place multiple designs on the same mask/wafer, thus dramatically lowering the costs low-volume designs.

The mask CoO numbers from the various optical and NGL technologies are surprisingly close, and the differences are well within the error bounds of the estimations. Clearly, lithography masks are indispensable. DRAM and MPU makers may be willing to accept masks no matter what the price, but can the ASIC and SOC? What should not be overlooked is the technological value being brought to the table. Perhaps timing rather than cost or feasibility will be the final judge.