Ball Grid Arrays: the High-Pincount Workhorses

		At a Glance
	Most microprocessors, graphics chips and ASICs are packaged in ball grid array (BGA) packages. These devices have too many I/Os to use a peripherally leaded package on the board, and thermal requirements that cannot be handled by a CSP or direct chip attach. Moving to flip-chip attach inside the package has both economic and performance advantages, but it is still only used for higher-performance applications.

Peripherally leaded packages, such as quad flat packs (QFPs), are cost-effective vehicles for semiconductor devices until the pin count goes above 200. Area array interconnection schemes take over above 200 pinouts because they take less board area, often with a much more relaxed I/O pitch. For years, pin grid arrays (PGAs) have been used for advanced, large I/O devices, such as the 80486 processor, and they still are. But now, the ball grid array (BGA), the surface mount variety of area array packages, is the package of choice for these devices (Fig. 1).

BGAs come in sizes below 200 pinouts, and many chip scale packages (CSPs) have the form of a BGA. Saving space on the board is typically the driver for going to one of these packages. The current drive toward system on a chip (SOC) likely will increase the number of packages with pinouts over 1000, requiring one of the enhanced BGA designs.

BGAs come in a variety of configurations and material sets. The die-up configuration is most popular, while cavity-down configurations exist for devices with greater thermal management requirements. Most use the classic die bond and wire bond scheme for the first-level interconnect, while some of the more advanced devices are flip-chip attached. Package substrate materials vary to optimize cost, thermal management, moisture resistance and interconnect reliability at either the first (chip-to-substrate) level or second (package to board) level. Many multichip modules (MCMs) come in the form of BGAs.

Land grid array (LGA) and solder column array packages are related to BGAs. For BGAs, solder balls are attached to the package before board assembly. For LGAs, the solder can be applied to the board instead, though wire springs and conductive polymers are more prevalent. Using solder columns is an extension of using solder ball connections, and it typically is done with ceramic substrate BGAs to add reliability to the board connection.

Fig. 1 BGAs are the workhorse for larger-pincount ICs. Pictured is a 388 ball BGA package. (Source: Abpac)

Chip interconnection

Most packages use die bonding to attach the die to the substrate and make electrical connections between them. This is the case with BGAs, but more of them are using flip-chip interconnection. With the flip-chip arrangement, a heat spreader can be attached directly to the die for heat removal.

Much engineering has gone into wirebonding for BGAs. Not only are the wirebonds made with pitches down to 50 mm, but the wires must have low loops with engineered shapes (Fig. 2).¹ These shapes have a sharp turn in the wire right after the first bond to keep the loop low. In cavity-down packages the loops also may have bends in the middle to keep the loop height even lower. With the presence of ground and power rings, extra bends often are required near the second bond to ensure the wire clears the rings.

Tape automated bonding (TAB) is used to some degree in BGA packages, including Tessera's mBGA chip scale package. But its use in larger-pincount BGAs is limited.

Fig. 2 Wirebonding in BGAs requires a good deal of wire loop shaping in addition to managing tight pitches and achieving high speeds. (Source: Kulicke & Soffa Industries)

Flip-chip interconnection has been gaining acceptance for higher-performance devices and should gain more acceptance as the number of high-performance devices and systems on a chip increase. In fact, many agree it is cheaper to implement flip-chip attach. Wirebonding is proven, and many are simply getting all the use out of their existing wirebond equipment that they can.

Joe Battaglia of Speedline Technologies said, 'If IC companies go to an array technology for first-level interconnect, through evaporative, plating or screen printing technologies, there is a huge cost savings to be made for them. That unfortunately requires them to break with the past with wirebonders, which is something they are unwilling to do, because they work. That is a challenge for the industry.'

Substrates

BGA substrates perform several functions: signal and power distribution, thermal conductance, CTE matching to the board. In many cases, building up substrates to add power planes helps shield signals and add thermal conductance capability.

The coefficient of thermal expansion (CTE) is an important consideration in choosing a substrate. Silicon has a CTE of ~2.8x10^-6/K, while typical laminate PC board materials have a CTE around 18x10^-6/K. Ceramic substrates with CTEs around 7x10^-6/K match better with silicon than laminates, but they don't match well with PC board materials. Laminate substrates match well with the board, but not with the die. Where the CTE cannot be matched well, encapsulants, underfills, die bond materials or special methods must take up the slack.

In most cases, it is cost-effective to use a laminate substrate to simplify second-level interconnect, and use die bond or underfill materials to absorb the CTE mismatch at the first-level interconnect. Most organic laminate materials are made of bismaleimide triazine (BT), or a BT impregnated glass weave. The Pentium II processor core uses flip-chip attach with underfill on an organic substrate. Attaching the processor core to the module board requires no enhancement.

Fig. 3 Substrate materials, such as this reduced CTE organic, are an important element in BGA design. (Source: IBM Microelectronics)

Tape, or flex, substrates are used in many chip scale BGA packages. Many times this is a two-layer tape with a single metal layer. AlliedSignal Substrate Technology & Interconnects (ASTI, Costa Mesa, Calif.) is offering a tape substrate with 100 mm pad size and 25 mm metal trace size capability. ASTI also offers a multilayer organic substrate that uses a tin-copper ink technology to join the layers.

Ceramic materials are used to enhance the reliability of the first-level interconnect. Low-temperature cofire ceramics (LTCC) are being used more often to allow the use of copper traces and integrated passives.

Generally, ceramic substrates larger than 35 mm suffer reliability problems due to CTE mismatch with the board. In some cases, special boards are used. To attach a larger ceramic package to an organic board, solder columns are used instead of solder balls to make a ceramic column grid array (CCGA). The longer shape improves the fatigue life of the interconnect. Also, Kyocera developed a dimpled ceramic substrate for BGAs that uses solder-filled dimples to effectively extend the height of the solder ball.

John Knickerbocker, director of Interconnect Product Development for IBM's Microelectronics Division, said ceramic materials optimize chip-to-substrate reliability, while an organic substrate would optimize surface mount reliability. 'What you are doing is making sure on both sides, both chip to substrate and chip to board, that you meet the customer's applications space,' he said. He went on to say die size and wireability determine the choice of a substrate. 'You've got to look at the ability to capture various die sizes and the I/O density. Beyond the number of I/Os, one has to be able to wire out those I/Os to the bottom surface of the chip carrier and then through to board. The wire density and the number of layers and fanout that one can achieve is also a factor in comparing the two types of chip carriers,' he said.

IBM Interconnect Products recently introduced an organic substrate, called a high-performance chip carrier (HPCC), with a CTE of 12x10^-6/K. It has a closer match to silicon than most organic-based substrate materials (Fig. 3).

W.L. Gore (Eau Claire, Wis.) has a substrate material, Microlam, made of expanded PTFE that is impregnated with adhesive and reinforcing filler materials. It is CTE-matched to copper in all three directions, which keeps stresses from building up within the substrate. The company demonstrated 20 mm lines on a 50 mm pitch, and 110 mm pad sizes.

Gore has done work modifying its substrate cross-sections to produce differing CTE zones. The CTE under the die then can be matched more closely to silicon. Other companies have looked into this general concept, but very little has been reported.

Siemens (Austin, Texas) recently released its plastic stud grid array (PSGA) package, which resembles a BGA. The substrate, including the interconnect studs, is molded out of plastic as one piece. The substrate is then plated with copper and covered with tin. The tin is patterned with a laser, and it acts as an etch mask for the copper. Electrical connection to the board is done with the copper coating on the studs. The laser patterning method is very fast and the substrates easy to make.

X-LAM Technologies (Milpitas, Calif.) has a thin film substrate technology, which is currently capable of 54 mm via pad designs. The company claims feature size capability down to 16 mm. The technology uses flat-panel display manufacturing equipment to process the substrates in large panels, which is the reason given for the feature size capability.

Alpine Microsystems (Campbell, Calif.) has adopted a silicon-on-silicon technology. The first level interconnect inside the package is flip-chip on silicon. This technology is intended for multichip module (MCM) packages, regardless whether they are BGAs.

Package design

Package design is an increasingly important aspect in successful BGA packaging. Not only is there a wider variety of materials to choose from, but there also is an increasingly complex set of devices to package. More are recognizing that designing the chip and package together is important. Some even take the board into account when designing the chip.

PC Board Thermal Conductivity
Board Type			Thermal conductivity, W/m-K
Two-layer, 5% Cu			0.75
Two-layer, 25% Cu			3.0
Two-layer, 50% Cu			5.6
Four-layer			13.4

Some companies provide software specifically for designing BGA packages. CAD Design software (Santa Clara, Calif.) offers a package called Electronics Package Designer (EPD), with a suite of plug-in applications, that works with AutoCAD for designing packages including BGAs. PADS Software (Marlborough, Mass.) recently released its Power BGA product for designing BGAs. Avant! (Fishers, N.Y.) has a design package called Encore BGA, and a product called Encore PQ intended to let chip designers quickly determine the feasibility of a package idea. Cadence (San Jose, Calif.) recently announced its Advanced Packaging Ensemble, which includes contributions from Pacific Numerics (Scottsdale, Ariz.).

The basic thermal enhancement principles in BGA design include the use of heat spreaders and heat slugs. Copper power and ground planes in multilayer substrates contribute to the package's thermal conductivity. Also, it makes little sense to use an enhanced BGA if the PC board to which it is attached cannot handle the thermal load. Adding layers to the board adds complexity, but it also adds greatly to thermal performance. Using a four-layer board instead of a two-layer board can increase the board's thermal conductivity up to four times (Table).² Basic electrical considerations in design are the dielectric constant of the substrate, controlling impedences and reducing parasitics. Using ground and power rings around the die helps reduce inductance in the power supply to the chip, as does using power and ground planes in the substrate. These structures help against ground bounce and related problems. Also, the signal traces often are engineered to have a 50 W characteristic impedence throughout the package.

In conductor designs that require gold plating, the electrical characteristics of the plating tails must be taken into account. Paul Wu of Unicap Electronics Ind. Corp. (Taiwan) said, 'Plating tails waste valuable routing real estate and hurt electrical performance, as they act as antennas and extra capacitances for high-speed lines.' A subtractive technique, gold pattern plating, avoids plating tails. Gold is plated onto the copper before patterning. The gold is patterned and used as an etch mask for the copper.

Fig. 4 Many CSPs have the form of a BGA, but only some of those are considered to be 'real' BGAs. (Source: Techsearch International)

CSPs

Many chip scale packages (CSPs) come in the form of a BGA. This is done to save space, so the device can be a chip scale device. Many are quick to make a distinction between these CSPs and BGAs. According to Lee Smith of Amkor, packages with ball pitches less than 1.0 mm are classified as CSPs, and packages with ball pitches 1.0 mm and larger are BGAs. Smith said: 'OEMs prefer this classification vs. the outdated JEDEC 1.2 times die size definition because the total cost and design choice is more dependent on ball pitch vs. die size. Also, they don't want to have to document and suffer design or tooling changes for each die shrink associated with a true chip size package.' Smith also noted that for higher pincounts, OEMs have to use microvia technology or additional PCB layers to escape route array pitches below 1.0 mm.

There also is some debate as to how much of a package some of these CSPs are. Though they all may fit a minimum definition of a package, they do not all fit everyone's definition of a complete package. Fig. 4 shows one breakdown between CSPs and BGAs.

New challenges

One of the new challenges in packaging technology in general is stacking die. This is finding its way more into CSP memory packages, but it is a growing trend that can include any multichip package.

Fig. 5  The different types of BGA packages have their strengths, suiting them for specific application requirements.2

Another future challenge is packaging a thinner die. Some view this as a way to implement die stacking without extending the vertical profile. It also is a way to improve first-level interconnect reliability. A silicon die with a thickness 100 mm is flexible and resistant to cracking, if grinding damage is removed. A flip-chip with this thickness can flex to take up CTE mismatch. Mechanically, this would be an advantage, though there are questions about electromigration in the on-chip interconnects when the die is flexed.

The most pressing challenge is in using high-density interconnection. Right now, flip-chip pitches are hovering around the 200-250 mm area. This inevitably will shrink, and substrate routing technology will have to match the shrink. Filling vias with diameters below 100 mm also will be a challenge. These challenges will not only have to be met in the package, but also on the board. Johnson Matthey Electronics (JME, San Diego) recently developed a high-density interconnect via fill material, JM3201, for this application.

Conclusion

BGA packages often require more PC board layers than their peripherally leaded counterparts, but the board area savings makes up for it for devices with 200 or more pinouts. Also, these higher-performance devices need the extra thermal enhancement that comes from using a multilayer board, whether a BGA is used or not.

Each type of BGA has its strengths in terms of cost and performance. They should each be examined for each new application. One breakdown of the relative strengths and weaknesses of the various kinds of BGAs is shown in Fig. 5.² BGAs and their related packages should see continued use for large I/O applications such as microprocessors, graphics chips and systems on a chip.

References

1. L. Christie, L. Levine, M. Eshelman, 'Bonding BGA Packages Requires Integrated Solutions,' Semiconductor International, July 1998, pp. 311-318.
2. T. Tarter, M. Goetz, M. Papageorge, 'Ball Grid Array Performance Characteristics: A User's Design Guide,' Surface Mount International Technical Proceedings, San Jose, Calif., August 29-31, 1995, pp. 245-254.