IBM Announces Open On-Chip Bus Architecture

-- Semiconductor International, 8/1/1999

IBM (Fishkill, N.Y.) has introduced an open on-chip bus architecture called CoreConnect that is compliant with Virtual Socket Interface Alliance (VSIA) guidelines and immediately available--at no licensing or royalty cost--to chip designers and core IP and tool developers. IBM also announced formation of the CoreConnect users group, a consortium of leading IP and service providers, led by Mentor Graphics Corporation and Cadence Design Systems, Inc., who have adopted the CoreConnect bus and plan to work with IBM to drive its continued evolution.

CoreConnect provides a method for assembling pieces of chip designs from diverse suppliers and facilitates an open system-on-a-chip design process that encourages development of reusable IP, according to IBM officials. In making it freely available, IBM said it believes it will be a de facto bus standard. It has served as a foundation for more than 20 chip designs over the last two years using cores from the IBM Blue Logic core library, IBM said.

The IBM CoreConnect bus includes the processor local bus (PLB), on-chip peripheral bus (OPB), a bus bridge, two arbiters and a device control register (DCR) bus. High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB, resulting in greater overall system performance.

IBM is licensing the arbiter and bridge macros, bus monitors, and bus functional language compiler of 32- and 64-bit versions of CoreConnect at no charge.