TSMC Ships Commercial 0.18 µm Devices

-- Semiconductor International, 8/1/1999

Taiwan Semiconductor Manufacturing (TSMC) has started the first production of devices using its 0.18 µm process. It claims to be the first fab to bring a copper interconnect technology line to such an advanced state. It will now spend $1B in fiscal year 1999 to bring its new capacity on-stream instead, up from $600M scheduled just a few months ago.

Andy Shen, managing director of TSMC in Europe, said: 'We are already shipping products, for instance to customers that supply three-dimensional graphics chips and devices for set top boxes and wireless communications. This means that we have caught up on the process technology road map with chip makers such as Intel. We will be in volume production with our in-house-developed 0.18 µm process at about the same time as these companies and will certainly be ahead of rival foundries.'

He added that the market has picked up and that TSMC has increased its customer base. By the end of this year, TSMC will have a capacity of 34,000, 200 mm wafers per month using its 0.18 µm process. It expects this capacity to increase 10-fold in the following two to three years. Shen said TSMC's 0.18 µm process is a 'true' technology that not only has CMOS FET transistor gates with a drawn 0.18 µm dimension, but also layout and interconnect design rules appropriate to this generation. Although the revised SIA roadmap omits the 0.15 µm dimension, TSMC will continue to offer that generation.