Exploring the Limits of Cu/low-k Interconnect Performance and Die Yield

-- Semiconductor International, 8/1/1999

T he benefits of using copper and low-k dielectrics begin to diminish at the 0.1 µm (100 nm) process node where GHz switching speeds are the goal. A recent study by researchers from Bell Labs, Lucent Technologies (Murray Hill, N.J.) shows that optimization of interconnect RC delay dictates interconnect pitches 2-4X larger than the minimum scaling dimension, even when copper and low-k dielectrics are used. Using a high-density logic circuit, the researchers quantified the impact of increasing pitch on die size and die yield in a paper presented at the IITC (International Interconnect Technology Conference) in San Francisco in May.

The researchers assumed seven levels of copper wiring with 5 nm barrier metal and low-k dielectric (k = 2) and estimated issues related to packing five kilometers of interconnect on a chip a few square centimeters in area. They compared three interconnect architectures: using tight design rules (250 nm) for all levels except the top (520 nm, or 2X); using tight dimensions on M1-M3 and 520 nm on M4-M7; and using a reverse-scaling approach with M1-M3 at 260 nm, M4 and M5 at 520 nm, and M6 and M7 at 1040 nm (4X).

The hypothetical random logic circuit was constructed entirely of 3-input NAND gates, which occupy a 2.5 µm x 4.0 µm or 10 µm~ area at the 100 nm node. Figure 1 shows the impact of increasing line spacing on block dimensions at two critical levels with different spacing. MT(x) is denser than MT(y), leading to a 7% and 24% increase in y block dimension with spacing increase from 1-1.5X and 1-2X, respectively. MT(y) changes in pitch from 1X to 2X only caused a 2% increase in x dimension. Above 2X increases in x and y dimensions increase die area by 27%-34%.

For logic devices, the researchers used Rent's rule to estimate the number of signal I/O terminals as a function of the number of logic gates, T = kN^p, where k is a constant related to device type, N is number of gates and p is an empirical constant between 0.5 and 1. They combined Rent's rule with analytical expressions for interconnect length distribution by Dave, De and Meindl, and estimated interconnect delay using:

T_int = R_oC_w + 0.4((R_wC_w)^1.6 + (tof)^1.6)^1/6
+ 0.7R_wC_in

where R_w and C_w are resistance and capacitance of the wire, R_o is the output resistance of the driver device and tof is the time-of-flight of the electromagnetic wave of the interconnect. The first and last terms approximate the time required to charge the capacitance of the wire and output device, respectively. From these assumptions, the researchers optimized RC delay and capacitive loads for the hypothetical circuit.

Fig. 1 The denser line spacing of MT (x) has a greater impact on logic block dimensions than the MT (y) level.	Fig. 2 Effect on yield is considerable even with only a 10% increase in area.

The interconnect delay results (Table) indicate that the highest toggling speeds(L1 GHz)require optimization of interconnect spacing between 2X and 4X of minimum design rules for the global and semi-global interconnect levels (i.e., reverse scaling), along with significantly larger driver devices. For relatively short interconnects (1mm), RC delay contributes about 10-15% of total interconnect delay, partially die to the use of copper and low-k dielectric. For longer interconnects (4mm), RC delay dominates when minimum lines and spaces are used. Interestingly, though RC delay for wide wires is lower, the R_oC_w term increases for the 8X structure due to increased interlevel coupling.

To estimate the effect on die yield, the researchers assumed defects do not propagate from one metal level to another, so yields at each level can be multiplied together to give total interconnect yield. Using Poisson's distribution for defects (Y = e^-DA), with defect density, D, a function of linewidth and spacing, and assuming killing efficiency is inversely proportional to the line/spacing size, number of good dice per wafer for the 7-level interconnect results. Figure 2 shows the die yield loss using the reverse scaling architecture, comparing no area increases with 10%, 20% and 30% increases that result from using 2X-4X dimensions. As shown, the benefits of reverse scaling rapidly diminish if die size increases by more than 10%. To avoid large die area increases, more metal layers can be added, yet accompanying increases in cost of processing and cycle time are undesirable.