Via Fill Polymer Resists Moisture Aids Thermal Conductivity
John Baliga, Associate Editor -- Semiconductor International, 8/1/1999
PADS Software (Marlborough, Mass.) announced that
the newest version of its design software, PowerBGA 3.0, includes
flip-chip design tools, a physical design reuse (PDR) module and expanded
constraint-driven design capabilities.
RF Micro Devices (Greensboro, N.C.) announced it
has established an integrated multichip module assembly facility to
complement its wafer fabrication and testing capacity. The facility will
allow the company to assemble RF modules using both silicon BiCMOS and
GaAs HBT technologies, and perform global design of those modules.
ACX Technologies Celeritek Inc. Toshiba Corp. HEI Inc.
The
Advanced Polymer Group of Johnson Matthey Electronics (San Diego, Calif.)
recently developed an electrically conductive via-fill polymer material for
package substrates and PC boards that is designed to resist moisture and add to
the circuit's thermal conductivity properties. According to Bernard Ho, the
group's marketing and technical services manager, interconnect densities on
substrates and boards are increasing to the point that both require advanced
via-fill materials.
Company News
OnQ Technology
Inc.
is the new name for the company created
by the merger of Surface Mount Taping Corp. (SMT, Austin, Texas)
and Cofer Corp. (San Jose, Calif.). Its headquarters will be in
Austin, Texas.
(Golden, Colo.) plans to spin
off Coors Ceramics Co., creating a separate, publicly traded
advanced materials company.
(Santa Clara, Calif.), announced
its CMM1530-LC PCS power amplifier is now available in a 4 mm u 4 mm u
1.65 mm, plastic leadless chip carrier (LCC) package. It operates in the
1.85 to 1.91 GHz range on a 3.0-volt supply.
(Tokyo) announced it has
developed a new five-pin package, the ESV, that measures 1.6 mm u 1.2 mm u
0.55 mm.
(Minneapolis) obtained an exclusive,
worldwide license to manufacture and market a new high-frequency chip
carrier, VIA/BGA, for applications in local multipoint distribution
services (LMDS), ultra high-speed Internet routing and satellite
communications. It is a ceramic-based chip carrier developed for
applications in the 2GHz to 40GHz frequency range. The technology, and the
associated substrate technology, VIA Plane, were developed by Micro
Substrates Corp. (MSC, Tempe, Ariz.) and its parent company,
Circuit Components Inc. (CCI). HEI also announced a cash equity
investment of $1.5 million in MSC, and HEI plans to supply goods and
services, such as thin film substrate processing, to MSC beginning in
October. 
The material, JM3201, is a solvent-free, modified cyanate ester paste. Cyanate ester materials are very hydrophobic. The modification 'covers' the polar parts of the molecules to reduce moisture absorption, which is low in both the cured and uncured states. The cyanate ester base was chosen for its adhesion to the copperplating in vias, high Tg and high stability. The group has produced data showing a post-cure strength of 14.7 kg to copper, which only shrinks to 11.4 kg after exposure to 85° C/85% RH. The group reports 'industry standard' values to be 5.2 kg and l 1 kg, respectively, and claims it has strong adhesion to organic laminates as well.
Also, it is stable enough to do away with solvents, which reduces voiding shrinkage during cure. At 165° C, the material loses l 0.25% by weight. Shrinkage, in combination with the strong adhesion, would lead to peeling of the copper from the via during cure. Also, a void would cause cracking during temperature cycling. The cure is a single-step oven cure, since there is no solvent to burn out.
The material also has a thermal conductivity of 1.7 W/m-K, as measured by ASTM method E1530, compared to the 'industry standard' value of 1.1 W/m-K.
Via-fill polymers have advantages over solder. Since they can be screen
printed without a solder mask, they can be applied inexpensively with few
clogged vias. They also can fill high aspect ratio vias without 'solder
balling.' Materials such as these can help shrink interconnect sizes and
spacings for packages and boards while adding to their reliability.
More Agree to Unify Stacked CSP Standards
Hitachi, Ltd., Intel Corp., Mitsubishi Electric Corp. and Sharp Corp. have agreed to standardize specifications for stacked chip scale packages (S-CSP), for multiple memory modules. Sharp and Mitsubishi first proposed S-CSP specifications standardization last September.
In addition to the four companies entering into the agreement, five other firms plan to support the unified S-CSP specifications: semiconductor manufacturers Seiko Epson Corp. (Japan) and Sanyo Electric Co., Ltd. (Japan), as well as the assembly companies Mitsui High-tec Inc. (Japan), Amkor Technology, Inc. (U.S.A.), and Power Technology, Inc. (Taiwan).
The specifications are for flash memory and SRAM die stacked in one package. So far, 64- and 72-ball layouts with a 0.8 mm pitch have been specified with compatible assignments. Package sizes are 8 x 8, 8 x 10, 8 x 11 and 8 x 12 mm, with a maximum height of 1.4 mm.
