Clean Approaches for Dual-Damascene
Maria A. Lester, Associate Editor -- Semiconductor International, 8/1/1999
BOC Edwards Integrated Circuit Engineering Corp. Ashland-ACT Korea Ltd. (Pyongtaek City, Kyonggi
Province, Korea) has dedicated a plant to manufacturing advanced
photoresist strippers for the Asian microelectronics industry near Seoul.
The complex includes the manufacturing plant, administrative office, and
sales and service facility.
With the
emergence of copper and low-k materials, dual-damascene has been brought into
the forefront (see Dual-Damascene Challenges Dielectric Etch, pg. 68). This
process involves forming a trench in the dielectric and filling it with metal.
The particular metals used will affect cleaning options. Although there are
reports on Al dual-damascene technology, cleaning has not been addressed until
recently. Researchers at IBM Microelectronics (Hopewell Junction, N.Y.) and
Siemens Microelectronics studied the effects of wet etch and/or a sputter clean
prior to metal deposition on via resistance for 175 nm Al dual-damascene
structures (presented at the International Interconnect Technology Conference
(IITC) in May).
Company News
Lam Research Corp.
(Fremont, Calif.) shipped its 100th Synergy
Integra integrated CMP cleaning system to a major Korean DRAM
manufacturer. The shipment increased Lam's installed base of integrated
and stand-alone OnTrak cleaners to more than 750 systems worldwide.
(Wilmington, Minn.) entered an
agreement to buy the chemical management division of FSI International
Inc. (Chaska, Minn.) for ~$38M. Completion of the acquisition is subject
to various conditions, including regulatory approvals.
(ICE,
Scottsdale, Ariz.) released a new publication focused on the latest
advances in CMP processes and consumables. Topics include copper CMP,
low-k materials/CMP, copper deposition, polysilicon CMP and CMP equipment.
Information on market trends and process advancement also is included.
Three types of vias were studied: a 4:1 aspect ratio with Al vias landing on tungsten (W) damascene interconnects; 4:1 aspect ratio with Al vias landing on Al interconnects; and 1.3:1 aspect ratio with Al on Al interconnects. The researchers learned that the differences between the vias can be described by the differences in contamination layers following the resist strip. They also found that the type of via as well as the type of preclean determined via resistance. For example, it was determined that using either a wet clean or a sputter clean provided low via resistance in cases where Al vias land on tungsten. However, for 4:1 Al vias that land on Al, low via resistances were achieved only with a combination of wet clean followed by a sputter clean. For the 1.3:1 low aspect ratio Al vias landing on Al, sputter cleans alone provided low via resistance. These results showed that the low volatility of Al fluorides and the high thermal stability of Al oxides adversely affected resistances in cases where vias landed on Al, as compared with landings on W.
In another study from CEA-LETI (Grenoble, France) and EKC Technology Inc. (Hayward, Calif.), researchers investigated the removal of post-etch residues on dual-damascene structures with copper and a low dielectric material (SiLK from Dow Chemical). Dilute HF chemistry was compared with organic solvents cleaning processes (see Table). Dilute HF is usually used in front-end-of-the-line cleaning process. Here it is used to remove the post-etch residues and thereby reduce sidewall contamination. But using dilute HF produced poor results. A 10% critical dimension (CD) change for 0.3 µm holes occurred, decreasing the process window necessary to meet the 0.18 µm design rules of 0.1 µm lines and 0.3 µm space. In contrast, the aqueous/ organic chemistry provided a wider process window where the post etch removal was favorable.
SiLK was integrated into the process by replacing the traditional dielectric. This, however, created new cleaning problems. For example, during wet cleans, solvents penetrated the low-k material. The researchers then developed a new cleaning chemistry (CPX-50 from EKC), which was found to be compatible to SiLK and copper, and it also removes resist. A lift-off process for the resist was developed subsequently, targeting large areas and/or small isolated structures. The experimental CPX-50 was transferred to LETI for evaluation.
Although there will be many bumps in the road for full integration of
dual-damascene, preliminary results (etch rate on copper ~0.2 Å/min) of new
clean chemistries and clean techniques indicate continued progress to
dual-damascene processing.
| Table Organic Chemistry vs. Dilute HF Cleans | |||||
|
Analysis |
Before |
After EKC625 Cu |
After Dilute HF | ||
|
SEM |
Residues |
Clean |
Clean | ||
|
TEM |
Back-sputtered copper on sidewalls |
CLean Sidewalls |
Clean sidewall, CD loss (-10%) | ||
|
TOF-SIMS |
9 x 1014 atoms/cm2 |
9 x 1013 atoms/cm2 |
9 x 1012 atoms/cm2 | ||
|
TXRF on Blanket TEOS |
Contaminate defects at 1014
atoms/cm2 |
1012 atoms/cm2 |
1011 atoms/cm2 | ||
|
Via Resistance |
|
0.65 Ohm |
0.3 Ohm | ||
|
Source: EKC
Technology Inc. and
CEA-LETI | |||||
