Fewer Via Overetch Challenges in Dual-Damascene
Peter Singer, Editor-in-Chief -- Semiconductor International, 8/1/1999
AlliedSignal Electronic Materials
(ASEM) Applied Materials Inc. ASM Japan K.K., Mattson Technology (Fremont, Calif.) and CFM
Technologies (West Chester, Pa.) are working together to further
develop and market cleaning solutions for selected semiconductor
processing applications using dry and wet wafer cleaning systems. The two
companies will focus initially on optimizing wafer cleaning for post
implant resist removal with dry and wet cleaning.
Rodel, Inc. (Phoenix) and SpeedFam-IPEC
(Chandler, Ariz.) signed an agreement to jointly develop processes using
slurry- free CMP products from 3M. Initial work will focus on copper
processes on IPEC's 676 and 776 platforms, as well as shallow trench
isolation processes on a new web platform recently announced by
SpeedFam-IPEC.
Silicon Valley Group
Motorola
researchers, investigating ways to control problems associated with long via
overetches, found that copper dual-damascene processes have inherently less
variation than the traditional aluminum/SiO2 approaches.
opened a Low-k Integration Facility in
Sunnyvale, Calif., expanding its characterization and demonstration
capabilities to include multi-layer integration and high performance
packaging reliability testing.
(Santa Clara, Calif.) is
working with Silicon Genesis Corp. (SiGen, Campbell, Calif.)
to develop and commercialize plasma doping technologies for ion
implantation and other process applications. Silicon Genesis designs and
manufactures plasma immersion ion implantation equipment and offers
silicon-on-insulator wafer and process licenses.
a subsidiary of ASM
International N.V. (Bilthoven, Netherlands), has developed a new CVD
low-k dielectric process that produces a polymeric film with a high Si-O
content, yielding a k value of 2.7. The process, named AURORA 2.7, was
developed on ASM International's 200 mm Plasma Enhanced CVD tool, the
Eagle-10 Trident. The process named AURORA 2.7, was developed on ASM
International's 200 mm Plasma Enhanced CVD tool, the Eagle-10
trident.
(San Jose, Calif.)
completed the acquisition of Watkins-Johnson's (WJ) Semiconductor
Equipment Group. The group will be consolidated with Silicon Valley
Group's (SVG) Thermco Systems, creating a new subsidiary in Scotts
Valley, Calif., called Silicon Valley Group, Thermal
Systems. 
In work presented at the International Interconnect Technology Conference (IITC), the researchers explained how via overetch is determined by the thickness of the interlevel dielectric (ILD) being etched, the etch rate of the via etch process and the via etch time. In addition, the ILD thickness and etch rate vary independently and are controlled by completely different factors. The etch time is set such that, even with the known systematic and random process fluctuations, every via is functional and reliable every day. Thus, while the worst-case via is at the minimum etch time required, the best-case via can receive considerably more etch at the same time.
To better understand and control this range, the Motorola researchers studied two integration schemes: a conventional aluminum process with oxide and a dual-damascene process with copper. The results (Table) show aluminum-tungsten ILD thickness is controlled by oxide CMP, which accounts for 2/3 of the total variation in via overetch. Only a design change giving more uniform pattern density can improve the within-die variation.
By comparison, dual-damascene integration has inherently
less variation because it does not use oxide CMP. In a via-first scheme, the ILD
thickness variation is simply the deposited film uniformity. In a metal-first
approach, the via ILD is controlled by metal trench etch, which can be made very
uniform with a selective two-step process.
World's Smallest Contacts Etched
At International SEMATECH's Resist Test Center in Austin, Texas, Trikon Technologies Inc., Infineon Corporate Research, and Clariant GmbH have developed an enabling technology for definition and etching of the very small contact holes required for future advanced devices.
Trikon's Omega etchers were used, and an ICP high density plasma chamber dry developed the advanced 193 nm photoresist. A M0RI chamber was used to etch 30 nm contact holes as deep as 633 nm in PETEOS oxide -- far smaller than 140 nm contact holes required in year 2002 for the 130 nm technology node currently predicted by the Semiconductor Industry Association.
Infineon Technologies developed the advanced
deepUV/193nm CARL photoresist system, including a unique chemical biasing step
for definition of very small trenches and contact holes. Photolithography was
performed on a 0.60 NA 193nm microstepper using a standard binary contact hole
reticle. Clariant GmbH will commercialize the CARL photoresist in the third
quarter of 1999.
