Use Low-Current Measurements for Process Control
Timothy Turner, Director of Structures Engineering Semiconductor Division Keithley Instruments Inc. Solon, Ohio -- Semiconductor International, 8/1/1999
As semiconductor devices increase in complexity, dielectric thickness and gate lengths continue to shrink, making low-current measurements increasingly important for semiconductor process control. Measurement of currents and second order effects previously considered inconsequential are now becoming crucial. This includes measurement of transistor off currents -- including Gate Induced Drain Leakage (GIDL), Drain Induced Barrier Lowering (DIBL) and Stress Induced Leakage Current (SILC) -- and dielectric absorption effects.
Low-current sensitivity is especially evident in DRAM and flash RAM devices, where data lifetime is dependent on the rate at which a stored charge is diminished by leakage. Battery-powered devices also are sensitive to leakage. Even low levels of leakage current are a problem when a large percentage of transistors on a die are affected, and the problem gets worse as the number of transistors increases.
Low-current measurements also are important for high-speed logic applications. The underlying problem is parasitic capacitance associated with a logic device's metal layers. This capacitance becomes a limiting factor as the number of metal layers increase and device clock speeds approach 100 MHz. Ultimately, interlevel dielectric absorption puts an upper limit on the operating speed of the finished product. This becomes more evident as low-k dielectric usage grows. These dielectric absorption effects are most easily measured as slowly degrading low-level transient currents.
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Fig.
1 Transistor biasing and expected drain current characteristics
for typical GIDL measurements are shown. GIDL current increases with
higher levels of hot carrier stress in the transistor or higher gate field
stress in the gate oxide. |
Gate Induced Drain Leakage
Gate Induced Drain Leakage (GIDL) is leakage from the drain due to a high electric field in the small area where the gate overlaps the drain. This leakage is often associated with interface traps that exist when this electric field is present. The field is greatest when the transistor is off. For an n-channel transistor, leakage measurements are typically made with the source and substrate grounded, the drain forced to Vcc and the gate forced to ground. During device characterization, the gate can be swept from ground to some negative voltage while the drain current is measured.
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Fig. 2 The
leakage through a thin dielectric prior to and following a short tunneling
current stress is shown. When additional stress is applied, the leakage
value quickly saturates. The figure shows current density
(A/cm2), not actual
current. |
Figure 1 shows transistor biasing and expected drain current characteristics for typical GIDL measurements. This figure also shows the effect of electric field stress on the GIDL current. GIDL current increases with higher levels of hot carrier stress in the transistor or higher gate field stress in the gate oxide.
The magnitude of the GIDL current is proportional to the width of the test structure device. The greater the width of the transistor, the larger the area of gate/drain overlap and the greater the GIDL current. In short, low-current sensitivity is a function of gate width.
For example, consider a DRAM device with a stored energy of 0.02 pjoule, a gate width of 1 µm and a desired refresh time of 500 ms. Further assume that the capacitor has stored a high voltage and that the device state (signal) will not be identified as having the correct value if 50% of the total charge is lost. In this case, a GIDL current of 20 fA is sufficient to cause a loss of data in a single cell. This corresponds to a GIDL current sensitivity of 20 fA/µm of gate width. A typical test transistor with a gate width of 10 µm would be used to look for GIDL current in excess of 200 fA.
A different sensitivity might be calculated for a device intended for an implanted pacemaker with a battery. The battery is intended for 10 years of use, assuming a standby current of 10 nA. An additional leakage current of as little as 1 nA will then cause a 10% reduction in the life of the pacemaker. If the device contains one million transistors with an average gate width of 2 µm, then the maximum GIDL current density that can be tolerated will be 0.5 fA/µm of width. If the test transistor has a gate width of 10 µm, then the GIDL current must be verified to be <5 fA.
SRAMs are another application where GIDL current can be important. Consider a two-transistor cell on a 1Mb SRAM with a typical standby current of 10 nA. The average source current holding each cell in its set state is <10 fA. If the GIDL current in any cell transistor is >10 fA, the cell will fail. If the average transistor width for this cell is 1 µm, then the sensitivity level is 10 fA/µm. A test transistor with a gate width of 10 µm would have to demonstrate a GIDL current <100 fA.
Stress Induced Leakage Current
Stress Induced Leakage Current (SILC) is leakage through a thin gate oxide due to tunneling into and out of traps in the oxide. This leakage is measured using capacitor test structures. The leakage is induced by tunneling current stress in the thin dielectric and, therefore, is called Stress Induced Leakage Current. Figure 2 shows the leakage through a thin dielectric before and after a short tunneling current stress. When additional stress is applied, the leakage value quickly saturates as shown.
Figure 2 also shows current density (A/cm2), not actual current. Since test structures are rarely as large as 1 cm2, measured currents will be very small. For a test capacitor that is 100 µm x 100 µm, the current density of 1 pA/cm2 would translate to a measured current of only 0.1 fA. A damaging current density of 100 pA/cm2 would translate to only 10 fA on this small test capacitor.
SILC is very important in flash memory devices1. Flash memory and EEPROM devices are programmed with a tunneling current (the source of stress in SILC) and are designed to store charge for many years. Even though the area of a single cell can be very small, the charge stored on the cell is also small, and its lifetime is expected to be very long. A tiny leakage current will eventually cause charge loss and memory failure.
The thinner the oxide, the greater the SILC for any given stress. Rennion, S. Gladstone, et al. have shown the increasing effect of SILC on today's flash devices.2 SILC becomes the life limiting parameter for gate oxide thicknesses <50 Å.
The stress that causes SILC may be induced by a manufacturing process. For example, charge accumulated on a gate from ion implantation or plasma etching can induce a voltage on the gate sufficient to cause significant tunneling current. This can be the source of stress that causes SILC. Therefore, measurement of SILC is often the fastest way to determine the extent of damage from process-induced charging.
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Fig. 3 A normal
charging current pulse and a current pulse with dielectric absorption are
shown. Point A on the curve is the point at which the dielectric
absorption effect should be measured. |
The SILC measurement is generally made on a transistor connected to a charge
collection antenna structure. The antenna is a poly or metal geometry connected
to the gate. Each antenna is designed to be sensitive to one potential form of
process-induced changing. For example, a large extension of the gate poly placed
on top of the field oxide will act as an antenna for the source/drain implant.
Ions striking the poly during the implantation add one positive charge to the
electrically floating poly. In addition, the ions may splash off secondary
electrons that remove
-1 charge. The result is a rapid charging that is a
function of the surface area of the gate and antenna.
The voltage produced by this charge will be a function of capacitance. The capacitance of the poly-over-gate oxide will be much higher than the capacitance of the poly-over-field oxide. Therefore, the larger the size of the poly-over-field geometry, the higher the voltage induced by any given charge applied to it. Also, virtually all of the charge will tunnel through the gate oxide; only an insignificant percentage will tunnel through the field oxide. Therefore, it follows that the larger the poly-over-field oxide attached to the small gate area, the greater the stress applied to the gate oxide.
Thus, antenna transistors are built to be the most sensitive transistors to any charging effect seen in the fabrication process. The antenna ratio is used to calculate the sensitivity of the antenna transistor. (The antenna ratio is the ratio of the area of the antenna compared to the area of the gate.) Antenna ratios of 100 to 1000 are typically used in wafer scribe lane test structures to provide a warning if any step in the process begins to cause charge damage.
An SILC measurement can provide a fast way of measuring the extent of oxide damage caused by process-induced charging. Unfortunately, the large antenna ratio needed to provide sensitivity to damage often results in a requirement for a small test transistor. If an antenna can be constructed to be about the size of three bond pads (300 µm x 100 µm) and the specified antenna ratio is 100, the test transistor can be only 300 µm2. If the SILC is only 1 nA/cm2, then the instrumentation must be able to measure at least 3 fA if this measurement is to be used to detect process-induced charging.
Dielectric absorption
Dielectric absorption is caused by the movement of ions or alignment of dipoles in an imperfect dielectric material. This can be caused by ions of sodium in silicon dioxide, but is most pronounced in organic compounds. Generally, materials such as spin-on glass (SOG) and low-k dielectrics have a more pronounced dielectric absorption effect than high-purity materials.
When a voltage is applied to a conductor surrounded by a dielectric, an electric field is introduced into the dielectric material. Any mobile ions or dipoles in the dielectric can then migrate or align with this electric field. The movement of these dipoles increases the capacitance of the conductor.
Charge required to bring this additional capacitance up to the forced voltage will generate a very small current tail during the time the ions and dipoles are aligning3. This current is generally insignificant with regard to circuit operation, but the slow increase in capacitance associated with the conductor line may be very significant. If the conductor is rapidly switched to some different voltage, the larger capacitance must be switched at that moment.
For high-speed logic devices such as CPUs, the metal line capacitance can be a limiting factor in the ultimate speed of the device. This is especially true when materials such as SOG, TEOS (tetraethylorthosilicate) ozone deposited materials and the new low-k dielectric materials are used. These materials often have both higher and more variable dielectric absorption properties.
Dielectric absorption is most easily measured by observing the current following a sudden voltage step. Figure 3 shows a normal charging current pulse and a current pulse with dielectric absorption. The measurement of dielectric absorption is conducted by forcing a voltage on a metal finger capacitor with a large perimeter to attract ions. After waiting a short period of time for normal charging currents to settle out, the current still flowing in the capacitor is measured. Point A on the curve in Figure 3 is the point at which the dielectric absorption effect should be measured.
The biggest problem with dielectric absorption measurements in semiconductors is the parasitic dielectric absorption effect found in many instrument systems. The size of a fingered capacitor test structure is limited on a semiconductor device, and the dielectric materials are generally much purer than similar materials commonly used in electrical wires or cables. An instrument connected to the test structure through 4 feet of cable and 10 inches of conductor trace on a printed circuit board, and/or connected through a large switch matrix, will exhibit dielectric absorption significantly greater than anything that can be measured on the semiconductor device.
Instrument accuracy is only one small component of a dielectric absorption measurement. The cabling from the instrumentation to the device under test plays a prominent role in this measurement. This measurement can only be made if the dielectric absorption effect in the instrument and cabling is significantly less than the expected dielectric absorption effect in the device under test. Any measurement of dielectric absorption must be preceded by a characterization of the dielectric absorption effect in the instrumentation.
Instruments designed to avoid dielectric absorption will generally minimize the length of the cabling connection from the instrumentation to the test structure. They also avoid traces on printed circuit board material and wires insulated by organic materials (with the possible exception of Teflon insulation for short distances). For best results, the measurement should be made before further signal processing and routing through the test equipment's switching matrix.
Shielded or guarded cables will not prevent dielectric absorption. The
problem is caused by the movement of dipoles within the dielectric material. It
is a transient effect and has no dc component. Therefore, the techniques of
guarding and shielding commonly used to provide low-current resolution will not
prevent dielectric absorption. Guarding reduces the effect as it reduces the
electric field across the dielectric materials surrounding the conductor of
interest. However, the presence of ions within the material establishes some
small internal field that will show a dielectric absorption effect.
References
1. Kubota, K. Ando and S. Muramatsu, 'The Effect of the Floating Gate/Tunnel SiO2 Interface on Flash Memory Data Retention Reliability,' Proceedings of the Reliability Physics Symposium, 1996, p. 13.
2. Rennion, S. Gladstone, R. Scott, D. Dumin, L. Lee and J. Mitros, 'Limitations of Oxide Thickness in FLASH EEPROM Applications,' Proceedings of the Reliability Physics Symposium, 1996, p. 99.
3. Wang, T. Chang, L. Chiang and C. Huang, 'Field Enhanced Oxide Charge Detrapping in n-MOSFETs,' Proceedings of the Reliability Physics Symposium, 1996, p. 124.
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Timothy Turner is director of structures engineering in Keithley's Semiconductor Division, where he is responsible for design and development of wafer test structures and device reliability algorithms. He previously owned and operated Turner Engineering, specializing in accelerated test methods that allow reduced time to market, high stable yields and assured reliability for semiconductor fabs. His 20 years of experience in semiconductor reliability includes organizations such as the Reliability Analysis Center in Rome, N.Y. and Mostek Corporation in Carrollton, Texas. He has been issued six U.S. patents in the field of semiconductor processing and has published more than 25 papers in the field of semiconductor reliability and processing. |
