Dual-Damascene Challenges Dielectric Etch
Peter Singer, Editor-in-Chief -- Semiconductor International, 8/1/1999
Interconnects of the future -- at least the
near future -- will be very different from those commonly used today. Instead of
aluminum and silicon dioxide (SiO2), they will be made of copper and a material
with a low dielectric constant (low-k). This change is driven largely by the
desire to improve on-chip speed, which is limited by the resistance (R) of the
metal 'wires' that connect transistors, and the capacitance (C) of the
insulators between them. Copper has a lower resistance than aluminum, and low-k
dielectrics have lower capacitances than SiO2.
This switch from aluminum/SiO2 to copper/low-k involves a variety of fundamental changes in the back-end manufacturing process flow -- so many, in fact, that the industry is still sorting out what will work and what will not. 'If you look at the different types of etch hardware, the different types of low-k materials and the different process approaches you can use, you wind up with a large combination of possibilities on how to do the process,'' said Paul Winebarger of SEMATECH. 'They are all difficult, and it's not really clear which one is best.'
One thing is certain: since it is difficult to etch copper, a new approach called 'damascene' processing is required. In this process, a trench or canal is cut into the dielectric and then filled with metal. (The term is derived from the in-laid metal artistry developed in Damascus.) In 'dual-damascene' processing, holes or vias also are cut to connect one layer of metal to the overlying or underlying metal layer or transistor contact.
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Appllied Materials' Dielectric Etch IPS Centura system performs
the main dielectric etch step, photoresist and polymer removal, then the
nitride barrier removal in a single
chamber. |
- In the via-first sequence (Fig. 1), the via is masked and etched through the two layers of dielectric. The photomasking process for the subsequent trench etch must expose and cleanly develop a trench pattern in resist that has flooded the deep via. Typically, the via is covered by a photoresist or organic ARC plug that protects the via and the underlying via nitride. Then the trench mask is aligned with the via hole and etched through the top layer of dielectric stopping on the first nitride layer. Finally, the nitride is etched at the bottom of the via to expose the underlying copper line.
- In the trench-first process (Fig. 2), the trench is masked and etched through the top (trench) dielectric, stopping on the nitride layer, if a nitride stop layer is used. If an intermediate nitrite stop layer is not used, the etch system must be capable of very uniform etch with low REI lag together with a flat etch front. The via mask is aligned with the trench and etched through the bottom dielectric to the etch stop, if any, or to copper. The via mask must fill the trench.
- The buried-via (also called self-aligned dual-damascene) sequence (Fig. 3) combines the oxide etch steps but requires two separate ILD (interlevel dielectric) depositions with an intervening nitride mask and etch step. The lower (via) dielectric is deposited with a nitride etch stop on both top and bottom. The top nitride is masked and etched to form a via hardmask. This requires a special nitride etch process. Then the top (line) dielectric is deposited. Finally, the trench mask is aligned with the via openings that have been etched in the nitride, and both the trench and vias are etched in both layers of oxide with one etch step. This requires high nitride-to-oxide etch selectivity and near-perfect trench-to-via alignment. For this reason, this scheme is not generally being used.
The three processes proposed for dual-damascene differ in the sequence in which the via and trench are patterned and etched. The resulting structure is the same for all three. After etch, the combined trench and underlying vias are lined with the barrier (usually tantalum or tantalum nitride) and copper seed layers, over-filled with electroplated copper, and finally polished down to the top of the copper-filled trenches and the oxide surface. A blanket layer of silicon nitride is then deposited to cap the copper.
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Fig. 1 In the
via-first approach, the trench is patterned and etched after the via is
formed. (Source: Lam Research) |
Challenges with all approaches
All three approaches to dual-damascene present difficult lithography and etch challenges. In the buried-via/self-aligned scheme, for example, it can be extremely difficult to get good alignment of the trench with the hole in the hardmask -- easy to understand since it's buried beneath a layer of dielectric. If the trench and hole are misaligned, the via may no longer be round, but half-moon shaped, resulting in a high via resistance (assuming the smaller via can even be filled with metal).
Another lithography-related challenge in dual-damascene is that it can be tricky to pattern through thick layers of resist. This is especially true in the trench-first approach, as Mike Rice of Applied Materials explains: 'With trench-first, you need to get the resist down in the trench and then pattern the via within the thick resist. That's quite difficult. It can be done at 0.35 micron and potentially at 0.25 micron, depending on how good your lithography is. However, due to the difficulty, I don't believe it's something that will be around several years from now.'
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Fig. 2 In
the trench-first approach, the via is patterned after the trench. (Source:
Lam Research) |
For these reasons, many believe the via-first approach is emerging as the best solution. Yet several challenges must still be overcome.
One unanswered question is whether an intermediate etch stop layer is required to define the trench. Without it, the edges of the trench can be etched rapidly, leading to rounded edges (Fig. 4). Also, without an intermediate etch stop layer, etch systems would have to provide extremely good control of uniformity, to ensure all trenches are of the same depth across the wafer and from wafer to wafer. This could be difficult: since there is no real endpoint indicator, the depth of the trench can only be determined by the time of the etch. 'CD control of the trenches and depth of the trenches is going to be extremely challenging,' said Steve Crapps of Hitachi. 'The (low-k) materials may or may not lend themselves to that level of control.'
The third disadvantage is that the material commonly used for intermediate etch stop layers, typically silicon nitride, has a relatively high dielectric constant (k = 7), which can increase the capacitance of the dielectric stack. 'Even though intermediate etch stop layers are very thin, they can significantly impact the overall capacitance,' said Wilbert Van den Hoek of Novellus. In addition to being commonly used as an etch stop layer, nitride films are used as barrier layers on top of the copper layer, where they also add to the stack's capacitance. Although difficult, this scheme is running in production at IBM.
Equipment suppliers are working to develop films with lower dielectric constants as an alternative to silicon nitride. Novellus, for example, recently announced plans to supply a silicon carbide hardmask for next-generation devices, followed by a PSG film for the generation after that. Applied Materials also just announced a new silicon carbide-like material called BLOk (see SI July '99, pg. 28).
Another challenge associated with the via-first process is that this underlying nitride (or silicon carbide or PSG film) is typically exposed or 'open' at the bottom of the via, the entire time of the trench etch. To protect the nitride film, some have used a layer of photoresist or a spun-on antireflective coating. But Rice, of Applied Materials, says it's possible to avoid using such extra materials -- which can cause 'fences' and/or be difficult to remove -- by having high selectivity to the nitride. 'Without really good selectivity to the nitride, you wind up going through the nitride as you're etching your trench,' he said.
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Fig. 3 In
the self-aligned or buried-via approach, a hard mask is patterned and
etched. The trench and via can then be etched in one step. (Source: Lam
Research) |
After the trench etch is completed, the next step is to strip the photoresist and then remove the nitride at the bottom of the via to expose the copper. This nitride removal step can also be challenging: once the copper is exposed, it's important to not have so much energy in the etch that copper is sputtered up onto the sidewalls of the via (Fig. 4). If that happens, it must be removed before the deposition of the copper diffusion barrier, which would trap the copper on the wrong side of the barrier -- exactly where you don't want it. Another challenge here is if the via is slightly misaligned with the edge of the copper line. In that case (also shown in Fig. 4) a deep slit can be etched in the dielectric, which becomes difficult to fill with a barrier, again leading to copper diffusion problems. The trick to avoiding these problems is to have a high selectivity ratio between nitride and copper, and between nitride and oxide.
Yet another challenge is to integrate at least some of these various etch and resist strip steps in one tool. 'The via etch is performed first, followed by a trench etch and a nitride removal step. By integrating these processes, there's a huge potential savings,' said Rice of Applied Materials.
Asthana, of Lam, added: 'While these etches may be done on discrete tool sets, an integrated approach (in-situ etch in the same chamber) offers integration simplicity, and lower handling/wait steps, as well as overall cost-of-ownership advantages.' These associated etch processes include: (a) Organic ARC open (typically required for DUV resists), (b) In-situ photoresist strip, and (c) nitride finish etch.
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Fig. 4
Common problems in the via-first approach include rounding
of the corners at the bottom of the trench; sputtering of the copper onto
the via sidewalls during nitride removal; and hard-to-fill slits etched
next to the underlying copper in the case of
misalignment. |
According to Asthana:
- Organic ARC open etch uses an O2 -based plasma chemistry, and its key requirements include good uniformity (etch rate, profile and CD) and good control over CD bias.
- The O2-based in-situ strip provides strip rates L 3 µm/min with complete removal of photoresist in high aspect ratio via structures.
- The nitride removal etch is carried out immediately after the photoresist strip. The nitride removal etch parameters are controlled so the underlying copper is not oxidized or sputtered onto the sidewalls. In addition, this etch needs to have good selectivity to oxide so the overall CDs and profiles are not changed after the nitride etch.
Low-k trend
While most early implementations of copper in a dual-damascene structure have relied on silicon dioxide as the dielectric material, there is a strong drive to transition to low-k dielectrics. The problem is that nobody really knows what those materials will be, let alone what kind of etch requirements they might have. 'Through the next stage of technology, what we're going to have over several years running is a continuous transition from one type of material to the next,' said SEMATECH's Winebarger. 'We're going to have a period of fundamental changes in the dielectric coming every few years as we go to ever-lower-k materials.'
Low-k materials can be separated broadly into two groups: spin-on polymers and CVD-deposited organosilicate glass (OSG). 'There are two strategies out there,' said Winebarger. 'Some manufacturers are committing to some kind of CVD OSG material and using a spin-on polymeric material as a backup. Other companies are doing vice-versa: lining up some kind of polymeric spin-on low-k dielectric with some type of OSG film as a backup.'
Of course, a dual-damascene process involving low-k materials could be quite different from one based on silicon dioxide. According to Lam's Jackie Seto, 'The intermediate layers may not be the same with oxide and low-k damascene. Also, for low-k, hard masks may be required especially for organic low-k's. The buried-via process is not being used for oxide damascene. It is unclear at this time if it will be used for low-k. We guess that it will not due to alignment requirements at the small geometries.'
In practice, it's likely that different materials will be used for the dielectric at the via level and the trench level. Since most of the coupling issues that a lower-k material helps solve are encountered between adjcaent metal lines, the trench dielectric will be where the lowest-k materials are first used. The via dielectric is less critical from a capacitance perspective. 'The dielectric between the trenches is the most important for the overall k, so some people are putting a different material at the top than the bottom,' said Rice.
Etch equipment suppliers report that early investigations into the etch characteristics of low-k films show these films can be etched easily. The only challenge is that the etch chemistry may have to be tailored to match up with the amount of carbon, hydrogen, silicon, fluorine and oxygen in the film. 'If you've got a film that contains some carbon and hydrogen, and you change the composition of the film, we have to retune the process in order to meet the selectivity and etch requirements,' said Rice. Generally, the more carbon in the film, the lower the k value.
Conclusion
The move to copper and low-k dielectrics dictates a fundamental change in
back-end processing to dual-damascene. What makes the move particularly
challenging is that it is happening while the industry is also trying to move to
a larger wafer size and smaller geometries. But everyone seems to be taking it
in stride: 'Other than the fact that feature sizes are getting smaller, the
wafers are getting bigger, the materials are new and nobody has any experience,
I don't guess there are any real challenges,'' quipped one industry observer.
Perhaps Winebarger put it simply and best: 'The industry is pretty interesting
right now.' 
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