Aluminum Persists as Copper Age Dawns
Alexander E. Braun, Associate Editor -- Semiconductor International, 8/1/1999
For years, aluminum has been our industry's
metal of choice because of its ease of work and low resistivity. However, as
device shrinks progress and interconnect cross-sections get smaller, current
density has risen and electromigration become a concern. Second only to silver
in resistivity, copper has long been considered an option. Combined with
aluminum it provides added electromigration resistance, but raises aluminum's
resistivity. Now, device size, density and complexity make resistivity problems
impossible to postpone through ingenious design or stopgap measures (Fig.
1).
After a few false starts, the Copper Age is here.
'Current interconnect need is such that most of our customers are either in production ramps or putting in pilot lines for copper,' said John Chenault, executive vice president of the Metals Business Group at Novellus Systems, Inc. (San Jose, Calif.), Chenault believes the move to copper is well under way not just for the IBMs and Motorolas, but for smaller companies as well.
Dan Carl, general manager of Applied Materials' Copper Division (Santa Clara, Calif.) agrees: 'We're seeing advanced pilot lines and real copper production. By year's end we can expect 100,000 wafer starts or more per month.'
Carl believes current capability meets 3:1 and 4:1 dual damascene style structure needs; however, when low-k dielectrics (l 3.5) are integrated with very high aspect ratio structures, there will be hurdles unthought of at present. 'The real challenges are expected in two years when serious die shrinks come in,' he said.
 |
|
Fig. 1 The first new primary conductor in some three
decades, copper is likely to remain a staple for many years. It appears
unlikely a new material will appear any time soon that is capable of
replacing it and substantially imroving interconnect capabilities.
(Source: Novellus) |
But even rabid copper supporters agree it is too early to write aluminum's obituary. 'Aluminum isn't going away just yet,' said Andrew Clarke, CEO at Sputtered Films (Santa Barbara, Calif.). 'Many are still working in the 1 to 2 µm range. On fine features, they're still doing tungsten plug, and not looking for high-tech aluminum.'
Zheng Xu, Applied's general manager for the Plug and Aluminum Wiring Division, agrees. 'Aluminum interconnects will continue to be important for the low-cost, high-volume DRAM market.' He is quick to add that, for high-end microprocessors, the move is on to copper.
Xu does not see aluminum DRAM applications running out of steam until the 0.13 µm mark. 'Currently available microprocessors in the 500 MHz range use traditional tungsten plug and aluminum interconnect technology at the 0.18 µm node,' he said. 'Clearly, there's still considerable available aluminum horsepower for logic.'
Obstacles to copper
Although obviously bullish on copper, Novellus' Chenault is concerned about issues delaying the transition to copper. 'A big factor is the lack of design tools and people designing in copper. Many replace aluminum with copper in devices, without getting too many benefits because the device wasn't designed to be optimized in copper.'
Novellus believes most technical production challenges have been overcome. As Chenault put it, 'IBM and Motorola are already in volume production. Technically, nothing's keeping anyone from ramping up production. We're all on a learning curve. But, over time, costs will decrease and yields increase.'
The two main segments of the cost equation are interconnect layer and stack costs. 'A copper interconnect layer costs 20% less than a comparable aluminum one,' said Chenault. 'But copper's true cost-reducing value kicks in when you do something with six instead of eight layers. Two less layers translate into dramatic cost reduction.' This is why Novellus argues that until devices are designed from start to finish for copper, its significant cost advantages will remain unrealized. As Chenault put it, 'Going from a six-layer aluminum to six-layer copper device doesn't achieve copper's significant cost reduction.'
Memory will not abandon aluminum until the copper learning curve has been traversed and strong cost advantages can be realized. Chenault believes logic and memory manufacturers will want to have common back ends in their lines when it becomes cost-effective.
There are further hurdles, such as integration issues -- integrating the electrofill to do interconnects, and with the barrier seed. There are also CMP roadblocks for copper, similar to those once faced by tungsten. It is not just processes but materials that are different.
'We see three major changes coming in the industry that will change everything we do,' he said. 'Obviously, one is copper, the other dielectrics -- changing the oxides to a lower k -- and the third 300 mm.' Chenault is certain manufacturers will make the change to copper first, before tackling the others.
Around 2003 or sooner, adequate design tools should be available, and everyone will work with copper in one way or another. By then, dual damascene should be at the 0.13, possibly 0.10 µm node. 'We can run electrofill processes down to 0.13 µm CDs now,' said Chenault. 'Printing anything beyond that isn't possible today, and it's an open question how far we'll be able to push to the lower levels within a device. We may see a dual damascene logic structure with the first two layers of metallization, which uses CVD fill for copper, or some type of copper flow process in the upper metal levels using an electrofill interconnect.'
Another consideration is CVD tungsten plug technology, which will be available for both aluminum and copper. Tungsten contacts will be on the order of an 8:10 aspect ratio at 0.13 µm-level geometries -- very aggressive fills. This could require ionizing techniques to get titanium to the structure's bottom, as well as CVD-type barriers for tungsten. Novellus has in place a transition strategy for its INOVA product, which will enable it to go from PVD to an integrated PVD/CVD solution for HCM Ti CVD tinitride to extend the technology to tungsten plugs.
Choices or blind alleys?
Damascene promises reductions in process steps and costs, as well as processing equipment. As it develops, there will be a crossover point where copper is attractive due to the damascene process' cost savings, rather than speed or electromigration.
Some manufacturers view aluminum damascene as an intermediate step before copper; but Peter Butcher, Semitool's marketing director, believes the learning cost of coming up on aluminum is probably no higher than copper's, making it more efficient to change directly to copper damascene.
The state of the art is IBM and Motorola's full copper interconnect, especially for microprocessors and SRAMs, but some manufacturers are traveling a longer road. Recently TSMC announced its DL018 process -- four aluminum layers followed by two copper ones. 'This gets them into the technology; then they migrate it down into the chips,' said Semitool's Eudy. This option was considered previously; but early copper adopters chose the big change, did tungsten local interconnects then copper for the full set of interconnects.
Semitool views integration as a challenge. 'All processes must work together,' said Butcher. 'The IC manufacturer cannot just buy off the shelf. Integration work is required. He must evaluate the specific etch process with the particular barrier and seed and distinctive electroplating process, and his CMP process.'
While Eudy recognizes integrated solutions offered by some equipment makers can get manufacturers started in copper in record time, he sees a down side: 'Pre-integrated package solutions may limit you to a specific solution. This gets expensive if you have to buy a whole suite of equipment to get started and another new one if you want to make changes later.'
Semitool focuses on the ECD level and works with other manufacturers to adapt and integrate it with equipment of their choice. 'This works within limits,' admitted Butcher. 'But we have experience with a variety of vendors' equipment. We have over 30 tools in the field doing copper on over 20 sites, all using slightly different suites of equipment integration schemes.'
As shrinks progress, it is generally acknowledged that the seed layer is a weak link. 'The barrier will continue shrinking,' said Eudy, 'and at extremely small features in the future will become the driving issue. However, a more near-term issue is the seed layer's extendibility to ensure adequate feature fill performance. People frequently put up to 2000 Å on a flat field to get as little as 200 Å coverage on sidewalls -- and that's using some of the most advanced PVD equipment.'
Semitool views ECD as a long-term approach. As Eudy put it, 'The industry's roadmap is to do PVD or CVD barriers and PVD seed. The barrier may not migrate to CVD, but the consensus is that the seed layer will. We can achieve seed layer performance equivalent to CVD with ECD now. Our electrochemical seed layer process is competitive with CVD deposition and more cost effective.' Like Applied Materials, Semitool equipment provides a real-time closed loop bath analysis system. 'It is crucial to be aware of the effect of changes in chemical concentrations on process results,' said Eudy, 'and the effects of bath aging and electrolysis on the ability to analyze organic additives in the bath.'
ECD can deposit copper with grain sizes under 1,000 Å. 'This is comparable to a vacuum process,' said Eudy. 'But unlike it, after deposition the copper film's recrystallization process produced the large-grain crystal structure that provides better electromigration characteristics.'
The modular approach
Dan Carl, of Applied Materials, predicts that over the next two years some customers may prefer to buy pre-integrated sets of copper systems, including barrier seed, fill, and CMP, as well as an integration with low-k and in the dual damascene dielectric etch, providing a total copper wiring and interconnect solution (Fig. 2).
 |
|
Fig. 2 Advanced copper electromechanical plating systems
are equipped with integrated closed-loop electrolyte management systems
for close process control. The ECP shown in this picture is capable of
filling high aspect ratio vias (5:1) void-free with high throughput.
(Source: Applied Materials) |
'Each area has integration challenges -- for yield and electromigration,' said Carl. 'Manufacturers can't suboptimize on every piece of equipment and combination and permutation possible to determine what they get from a process. They're worried about integrating the overall back end and ensuring they can deliver reliable devices.'
Carl believes the industry also may opt to purchase smaller integrated process segments. 'The barrier seed, fill and CMP can be considered a process segment,' he said. 'Although there really are three pieces of equipment, users are beginning to consider this segment as a single tool -- or module -- balanced to the rest of the fab on yield, output, reliability, uptime, etc.'
This could fundamentally alter device manufacturers' thinking about how equipment should be supplied. If a fab has 300 to 600 steps, with 200 to 400 pieces of equipment -- each individually tailored to its particular process -- this is sufficient to keep busy a small army of integration engineers. 'If this changes to 50 or 60 modules,' said Carl, 'and customers are just concerned about each module's input and output, they could push the inside module migration work down to the equipment supplier and focus one level up on their value stream to their customers.'
It is no secret that major equipment manufacturers have R&D underway to integrate process control. In Carl's example, metrology would be key. Like most others, Applied's systems can be combined with common sof tware and hardware platforms, so achieving an adequate level of synthesis in diagnostics and control -- with in-situ or linked metrology -- is becoming necessary.
Integration considerations
Sputtered Films also does copper work. 'Currently, what we do is limited, but we have some great data,' said Andrew Clarke, adding that in work performed for Cu-Tek, 4:1 aspect ratio structures at 0.25 µm were filled. 'Companies lacking PVD have asked us to do seed layers so they can plate up with their tools or do CMP,' he said.
Although Clarke sees an irreversible shift to copper, he believes a dimension wall will be hit. 'It may be at 0.10 µm or 0.09 µm. Everything is pulling the fab's back end into the front end.' Clarke does not foresee difficulties with getting seed layers in. 'Problems will arise when they push the limits on how thin the silicon wafers can be made,' he said. 'The challenges will be in the back end handling and processing.'
Tom Seidel, CTO for Genus, Inc. (Sunnyvale, Calif.), believes a reality check is needed. 'The main challenge is found in the marketplace's status and reality. IBM and Motorola have pioneered copper with SiO2 in expectation of higher speeds and lower cost processes for 0.25 and 0.18 µm. Others are improving performance with design and packaging approaches for 0.25 and 0.18 µm, and looking to go to copper circa 2002 (0.13 µm) and 2004 (0.10 µm),' he said.
Seidel thinks today's limited-yield processes being done with PVD solutions are unlikely to extend to 0.10 µm. Genus, instead, has aimed its roadmap to CVD-based processes (Fig. 3).
'On the dielectric arena,' said Seidel, 'technologies compatible with existing copper will use Flare and Silk and initially settle for k values around 2.8 to 3.2. CVD processes using SiCxOywill be proven, but they're behind schedule, and organics already have one cycle of demonstrated success. The low-k segment may split into spin-on and CVD.'
 |
 |
|
Fig. 3 Figure 3a shows how the CVD WNx barrier and CVD Cu
seed layer provide conformal coverage in a high aspect ratio trench,
leaving a 0.05 mm wide, 30:1
aspect ratio trench to be filled with copper (Source: Genus). Figure 3b
shows the same feature, after ECD copper fill in Semitool's ECD reactor.
(Source: AMD) | |
'R&D for copper will focus on ultra-thin barriers, interface engineering (barrier to dielectrics and barrier to copper), and scaling of everything,' said Seidel. 'This includes scaling the thickness of the parasitic etch stop and hard mask layers. Of course materials with k values lower than SiO2will be included. Imagine the inorganic material of the 0.18 and 0.13 µm generation being used as etch stops and hard masks for the 0.10 µm generation!'
Measurement and characterization
Metal film measurement has been straightforward, with sheet resistance as a technique of choice. It has worked well; it is simple, cheap, fast, and precise to five significant figures if needed. But it is destructive, requiring physical contact with the films. Also, if several conductive layers are present, it measures the aggregate sheet resistance. Since this result is unusable to determine all the thicknesses, each must be measured singly. This has implications for monitoring strategies, particularly process modules involving depositions of more than one layer within the single vacuum system, such as Ti nitride on Ti and Al on Ti nitride on Ti. Here, five monitor wafers must be prepared and each individual deposition qualified.
Another consideration is that sheet resistance's relationship to film thickness, which is inversely proportional to thickness, degrades when films become thin relative to the electronic mean free path inside the metal being measured. The result's interpretation becomes complicated, depending on the electronic mean free path and factors like surface film roughness, interfaces and others. For titanium this begins at approximately 100 Å. For higher conductivity metals like copper, it occurs at greater thicknesses in the level of hundreds to a thousand Ångstroms. This is problematic for an increasing number of films. It was uncommon to put down 100 Å of Ti, or 50 Å of Ti nitride. It has never been common to put down 500 Å of copper.
Reliable measurement of CVD films' thickness is difficult because knowledge of bulk resistivity cannot be assumed.
Copper is worse. CMP damascene processes and tungsten films have the same problems -- namely, no metal should be deposited around the wafer's edge where it might hang over the bevel; otherwise polishing generates particles. This requires deposition control near the edges. Semitool copes with this by allowing copper seed layers to be deposited on the edge, for maximum area use du ring ECD. After ECD, the copper is removed in the edge's annular area. Analogous to a photoresist edge bead removal step, it eliminates copper at the edges and, as a result, associated particulate or flaking issues.
In other cases, film thickness measurements near the wafer's edge may be required, with a spatial resolution close to 50 µm between the bevel and approximately 3 mm from the edge.
Probe size makes this problematic for sheet resistance. A probe with small spacing between the electrodes is probably 1.5 to 2 mm across. Something 50 µm or less is required. Copper requires measurements on product wafers because plating rates and uniformity are subject to factors such as electrode contact repeatability, so events may take place on product wafers that do not on monitor wafers.
CMP rates are another factor. They must be monitored all over the wafer surface; and patterned wafers are affected differently than monitor wafers by factors like chip size, open space between ILD regions, and copper linewidths.
With copper, everything has come to a head.
Robert Stoner, research professor of engineering and Humphrey Maris professor of physics at Brown University (Providence, R.I.), helped develop, with Rudolph Technologies (Flanders, N.J.) the picosecond ultrasonic technique (PULSE technology). It uses a laser pulse about 0.10 ps in duration, focused on the film's surface through a conventional lens. The spot can be as small as 5 µm and fits in a measurement structure 30 or 40 µm in size.
The pulse's energy causes minor thermal expansion, launching a sonar-like sound wave that travels down through the film. The wave goes through, bouncing off interfaces between films of dissimilar acoustical properties. The echoes alter slightly the metal's n and k optical constants, causing a measurable optical reflectivity change.
From the time it takes those echoes to return, and known sound velocity in the metal, the product of the two numbers provides the film thickness. The analysis has been used for as many as nine films at once.
The technique is non-destructive and non-contact, and measurements are made, with some signal averaging, at a rate of a couple of seconds per measurement point. It makes it possible to measure copper thickness, postpolish, by going to the wafer's edge and to the small residual islands of copper that are left after polishing.
n&k Technology Inc. (Santa Clara, Calif.), developed its 'n&k method' to characterize thin film structures of up to seven layers. The technique is based on broadband spectrophotometry, combined with spectral analysis incorporating the Forouhi-Bloomer dispersion equations for optical constants n and k. Eliminating the need to measure phase shift presents significant advantages: measurement simplicity, speed and sensitivity in the DUV. Enhanced system sensitivity results from the fact neither polarizers or analyzers are used.
The technique obtains spectral reflectance data from 190 to 1000 nm with 1 nm resolution in under a second and can characterize a wide variety of thin metal films, including copper, aluminum, tungsten and gold (Fig. 4).
MKS Instruments (Andover, Mass.), has characterized copper CVD using an in-situ quadrupole mass spectrometer (QMS) process monitoring system. It has a closed ion source and is pumped differentially with a compound turbomolecular pump. The system directly samples CVD atmosphere via a small orifice.
 |
| Fig. 4 Characterization of a thin film of TIN deposited on a silicon wafer. Figure 4a represents the measured (red) and calculated (green) reflectance spectra. Figure 4b displays shows the thickness and n and k spectra off the TIN film resulting from the analysis. (Source: n&k) |
 |
The copper CVD precursor is CuI (hfac)(tmvs), trademarked CupraSelect, a complex metallorganic compound containing fluorine, liquid at room temperature. During deposition it is vaporized then decomposes, depositing a copper film.
The mass spectrometer was calibrated so the peak argon height equaled the total process chamber pressure. The spectrometer signal for trimethylvinylsilane at amu 100 was found to be related linearly to reactant flow rate. Response time for reactants and products species was on the order of seconds. Process reproducibility could be assessed by monitoring the spectrum over time. This is useful for tool and process optimization. A feature of the mass spectrometer software is the capability to rapidly scan over an amu range, save each scan, then do playback in movie-mode. This 'scan-and-save' is used to characterize the deposition process to determine which peaks would be useful for process monitoring. Typically, 10 or fewer are used. The fewer the peaks, the finer the time resolution, enhancing the ability to capture abnormal transients.
The new age
The processing changes that are required by copper will force manufacturers to revisit the flow and integration landscape. After 30 years of aluminum, we have learned enough to enable us to focus on a unit process and understand how to optimize it. With copper, these processes must now be viewed as they once were with aluminum: as sequences rather than discrete steps. We will have to go back to looking at steps before and steps after, and not at a particular unit process, because we lack the necessary knowledge about prior and later steps. Sequences of events and flows will have to be considered because they are interrelated and because by focusing on just a small portion some of the subtleties required can be missed.
Copper's future seems headed toward CVD. Possibly IMP barriers, to coat with copper barrier materials walls of high-aspect ratio lines and vias and contacts. Seed layers will become thinner than currently predicted, which is in the neighborhood of 2,000 Å of copper and a few hundred Ångstroms of tantalum or tantalum nitride. These materials will become sub-100 Å. Within two years, seed layers will dive into the sub-thousand Ångstrom range. Silicides and refractory metals used to make them -- such as titanium, cobalt and platinum -- will linger because it is still necessary to make contact to the transistors at the bottom of the stack, which will not be done with copper.
Copper will remain with us for a long time. Dan Edelstein, of IBM, thinks it unlikely a new material will substantially improve interconnect. When copper's electromigration resistance becomes limiting, it may be necessary to add dilute alloying elements to strengthen it, such as tin, to raise electromigration resistance without significantly affecting resistivity.
We have begun the move to a new primary conductor that will be all-pervasive in the industry, changing how we do things. As often before, we will be putting out product while learning how to produce it.
Will it be an easy transition?
No.
Can we do it?
Most definitely, yes!
Talkback
Related Content
Related Content
SPONSORED LINKS
