Shallow Trench Isolation Poses New CMP Challenges

Staff -- Semiconductor International, 6/1/1999

The CMP step for shallow trench isolation (STI) formation is the most challenging CMP technology due to the large variation in pattern density on typical STI wafers. Recent progress in the areas of process optimization, CMP tool comparison, single-step STI CMP and defect reduction were recently presented at the 1999 CMP-MIC Conference in Santa Clara, Calif.

Exploring the effect of feature size and reverse photomask use on TEOS-oxide CMP removal rate, Marilyn Jouty of ST Microelectronics (Crolles Cedex, France), Maurice Rivoire of France Telecom/CNET (Meylan Cedex, France) and Thomas Detzel of Rodel Europe (Feldkirchen, Germany) determined that effective STI oxide removal involves the use of abrasive slurry particles of smaller dimension than the minimum device feature size. A slurry with particle size distribution centered at 114 nm used on 0.25 and 0.18 µm feature sizes offers 50%-80% faster removal rates than a slurry with comparably sized particles (centered at 360 nm) and features. Lower removal rate is due to abrasive particle trapping in the smallest features. A pre-planarizing counter mask reduces removal rate further, possibly due to geometric differences with the reverse mask approach.

James Schlueter, Inki Kim and Frank Krupa of SpeedFam Corp. (Chandler, Ariz.) emphasized the critical role of slurry and pad choice in minimizing trench oxide erosion (dishing) effects. They observed that while minor improvements can be made through process parameter adjustments, consumable type and treatment prove most important. High-selectivity ceria-based slurry provided reduced nitride erosion in wide pattern density areas of the MIT test wafers relative to silica-based slurries, while also reducing dishing in trenches. Pad conditioning changes offered little improvement, outweighed by negative process stability effects. In comparing five different commercial pad combinations, employing various sub-layer and pad grooving/perforation schemes, a fixed abrasive pad with a harder polishing surface produced slightly better nitride and trench erosion results, even with increased over-polishing.

Luther Peng and Champion Yi of ProMOS Technologies (Hsinchu, Taiwan) evaluated five CMP polishers for one-step STI planarization (Table). Polisher A's three tables enable use of different chemicals in each of the coarse polish, fine polish and buffing steps. Polishers B and C use new carriers with floating head designs. Polisher D uses a fixed abrasive pad (slurry-less) with KOH or DI water. Polisher E employs a semi-rigid polishing wheel with a low flow rate of CeO₂ slurry. Using 0.25 µm SDRAM short-loop patterned wafers with trench depth of 4500 Å filled with 6000 Å of HDP CVD oxide, DOE experiments determined the effects of down force and table speed on uniformity. Experiments revealed large differences in wafer center and wafer edge dishing in traditional rotary polishers. Polisher B is more effective in the edge area than polisher A, perhaps due to its larger polishing table. Polisher C featured equal dishing in center and edge areas, both dependent on the mixture of down force and table speed. High-selectivy slurry reduced the dishing effect, especially in large oxide areas.

Researchers from Hyundai Electronics (Kyoungki-do, Korea) optimized the filtration of ceria-based slurry to reduce the quantity and depth of microscratches to raise gate oxide yields to manufacturing-worth levels for 0.18 mm devices. In this study, slurry with high nitride:oxide selectivity improves the reliability of the polish stop on nitride layers, leading to lower thickness variation of trench oxide, whose non-uniformity problem can contribute to poly stringers after gate etch or broad threshold voltage variation. Using HDP-CVD oxide, oxide densification, CMP with a rotary polisher and dummy patterns to minimize dishing effects at high oxide removal rates, microscratches occurred and increased with polishing time. The optimized filtration method reduced the generation of microscratches, while the high-selectivity slurry offered suitable within-wafer, wafer-to-wafer and lot-to-lot uniformity for a manufacturable STI CMP process.