STI Update &n

Staff -- Semiconductor International, 6/1/1999

SI received a strong response to its April feature, "Choices and Challenges for Shallow Trench Isolation," encouraging this update of possible mechanisms for trench profile control and the effect on device performance.

Trench etch for shalow trench isolation.

Shallow Trench Isolation (STI) is a leading candidate for sub-quarter micron device isolation because it eliminates the LOCOS bird's beak and improves device planarity. In order for STI to be realized in actual devices, degradation of MOS transistor performance, caused by electric field crowding at trench corners, must be minimized. Engineers express concerns over trench shape, particularly at the bottom of the etched trench, as it can affect junction leakage by concentrating mechanical stress in the trench.

Profile control in most etch systems relies on changes in flow rate or ratio of etchant precursor gases, like Cl₂ or HBr. Some etch processes also incorporate oxidant sources, such as O₂ (or He-O₂), or N₂ for improved profile control. Yet another alternative involves the use of dual-frequencies in the etch reactor offered, for instance, on the Model 6510 HRe- etch system from Tegal Corporation (Petaluma, Calif.). Such a configuration allows adjustment of RF wafer bias to modify the balance between etching and sidewall passivation. The intent is to reduce profile microloading and trench depth non-uniformity. For more information, see the feature article, "Reactor Approach Investigates Masking Regime Impact on STI Etch," on SI's website at www.Semiconductor.Net.