SOI Technology Reviewed &nOpening at Plant

Staff -- Semiconductor International, 6/1/1999

SOITEC (Silicon-On-Insulator Technologies) opened the world's largest plant for the production of SOI wafers at Bernin in Grenoble, France. The company is now the first and only manufacturer in the world completely devoted to the production of SOI material. The new $50M plant incorporates a 15,000 ft² cleanroom area and exclusive wafer cleaning equipment from Shin-Etsu Handotai (SEH).

The new plant's production capacity is 200,000 wafers per year, increasable to 700,000 wafers per year to meet future demand. In addition to its manufacturing capabilities in France, SOITEC is actively working with SEH to implement a second SOI wafer manufacturing facility in Japan. The total production capacity of the two plants is projected to reach a million SOI wafers per year within the next three years.

André Jacques Auberton Hervé, corporate president of SOITEC, told Semiconductor International, that production at the Bernin facility is completely devoted to the company's UNIBOND process using its Smart Cut technology, but SOITEC has previously been involved in SIMOX (Separation by IMplanted OXygen) processing.

SOITEC also developed processes to create thin monocrystalline films of silicon on either quartz or glass wafers. These films are being used for the manufacture of small, high resolution LCDs and have better electrical characteristics than the polysilicon films widely used for this application. The driver circuitry can be processed on the same wafers so that connections to the thin film transistor matrix can be made more easily. Other uses include charge coupled device detectors and high-definition television projection systems. The Smart Cut process is not limited to silicon. SOITEC has collaborated with LETI and device manufacturers to produce 100 mm wafers of SiC/Si₂/Si and, for improved thermal conductivity, SiC/Si₃N₄/poly-crystalline Si. The company has also produced wafers of 50 mm diameter InP/SiO₂/Si layers. Conductive bonding via a metallic layer can be achieved with films such as GaAs/Pd/Si.

As part of its plant opening celebrations, SOITEC arranged a panel discussion on "SOI Technologies for the 21st Century." Here is a brief summary of the discussion.

• Dr. Jean-Luc Ledys, industrial coordination director of Gemplus (Gémenos Cedex, France), covered SOI use in smart cards with up to four chips in one card, which reduces 500 µm chip thickness to under 100 µm for the production of very flexible "cards" as plastic films. The films can be made very thin and uniform with SOI technology.
• Dr. Pravin C. Parekh, operations director at Honeywell Inc. (Plymouth, Minn.), spoke on SOI used to produce devices for high temperature operation. He said devices are shipped for use at up to 225°C, while others are designed for 300°C operation in oil drilling and other special applications. SOI can also be used to produce radiation hard ICs to achieve the next-generation device performance using existing equipment and that low power products will be the largest SOI applications.
• Dr. Seiichiro Kawamura, manager of Fujitsu's ULSI R&D division (Kawasaki, Japan), covered SOI use for ASIC logic device production. He said the SOI/CMOS ratio for logic might be at a point of inflection in an emerging market. Designs can be translated from bulk CMOS to SOI. They offer ultralow power consumption from supplies of <1 V for mobile communications and consumer devices. He said gate lengths of 0.18 µm, fabricated by KrF laser lithography using phase-shift masks, will fall to 0.12 µm next year.
• Dr. Shigeto Maegawa, SOI project manager, Mitsubishi Electric Corporation (Hyogo, Japan), spoke about the use of high-speed SOI devices in 10 - 100 MHz mobile communications applications. He said SOI ASICs could operate in the 0.3 W to 50 W range over the 20 - 400 MHz band.
• Dr. Makoto Yoshimi, SOI project manager, Toshiba Corporation (Kawasaki, Japan), described SOI used to produce very low leakage, low capacitance DRAM devices that are latch-up free and do not suffer from soft errors. He said SOI transistors with the gate connected to the body can operate down to 0.5 V, replacing SiGe with SOI devices can reduce the operating power by two orders of magnitude.
• Dr. René P. Zing, SOI project manager, Philips Semiconductors (Nijmegen, The Netherlands), said SOI offers a factor of two to three reduction in the device area in submicron, very thin, low power ICs. He foresees SOI applications in audio and automotive products for use at some 70 V. Philips (Hamburg, Germany) is using SOI to develop lateral rather than vertical bipolar devices. An important advantage will be the reduction of parasitic capacitances that will enable coils to be put on a chip.
• Dr. Theodore W. Houston, manager and SOI project chairman of the IEEE SOI conference, Texas Instruments (Dallas, Texas), reported on SOI use for high performance, low power microprocessors. He said the long-term view is that they will all be based on SOI and scaling will require double gate microprocessor transistor structures.
• Dr. Bor Yeu Tsaur, executive vice president, Kopin Corporation (Westborough, Mass.), demonstrated small, 0.24 in. diagonal displays with 80,000 pixels based on SOI technology. He said SOI technology allows high- and low-voltage devices to be integrated together on a chip. He suggested SOI will lead to portable information devices, including "wearable PC's."