Process development
Staff -- Semiconductor International, 6/1/1999
F lat panel displays based on field memission devices (FED) are becoming more accepted as an attractive alternative to liquid cystal displays (LCD) and plasma dislays (PD). FED-based displays offer increased brightness, improved viewing angle and reduced power consumption. 1 However, fabrication of FED displays on large area glass substrates presents new challenges for the patterning of the thin films. FED technologies require some geometries to be around 1 mm, which make their etch requirements similar to those of the wafer-based IC manufacturing. As a result, the use of wet chemistry for creating the FED structure often produces unacceptable results. Etch processes for FED fabrication have been demonstrated using conventional dry etching on small wafer-based samples. However, the stabilities of these processes on the large area glass panels that would be used in mass production have been largely unexplored. In this work, etch processes using a low pressure, high-density plasma etcher developed for use in a FED manufacturing line are described. Development work started by defining the etch processes on 6 in. round glass substrates, producing functional 5 in. FED displays. The processes were then transferred to a manufacturing line that used 370 X 470 mm glass substrates.
Process development
Fabrication of Spindt tip-based FEDs requires etching of the gate, insulator and cathode materials.2 For the initial process development, feasibility of the etches was demonstrated for molybdenum (Mo), oxide (SiO2) and amorphous silicon (a-Si), respectively. Patterning each of these films had different requirements in terms of etch rate, profile and etch selectivity.
The etches were performed in two different etchers. Etching of films on 6 in. round substrates was performed in a TCP 9400 polysilicon etcher that had been modified to handle the glass substrates. In the second stage of work, 370 X 470 mm glass was used as the substrate, and the etching was performed in a Continuum FPD etcher. Both etchers utilized planar inductively coupled plasma sources in order to generate high-density plasmas at low pressures.3
Samples of each size were etched and examined using SEM analysis. Etch rates for each of the processes tested were directly measured on partially etched films using a profilometer or optical non-contact film thickness measurement tool. Selectivity to underlying layers was estimated from SEM measurement or by completing a partial etch of the second material using the same process conditions. Amorphous silicon or dielectric films were applied to the glass substrates using a plasma enhanced chemical vapor deposition (PECVD) system. Molybdenum films were sputtered on glass substrates using an in-line sputter system. Photoresist was treated to achieve slope profiles for amorphous silicon and molybdenum etch profile samples.
Amorphous silicon etching
In FED manufacturing, patterning of the cathode material typically occurs first. For these tests, amorphous silicon film was used as the starting material to build the cathode structure. When patterning the amorphous silicon lines, a tapered profile for the amorphous silicon is usually desired to improve the step coverage of the insulating oxide layer that is deposited on top of these lines.
A chlorine-based chemistry was chosen for this application. High etching rates (>3000 Å/min) were achieved at process conditions in the range of 5-10 mTorr. Oxygen was added to the chlorine plasma to enhance the tapered slope of the amorphous silicon profile by increasing the erosion rate of the photoresist mask. A short native oxide breakthrough step was added at the beginning of the process to improve the etch uniformity and reduce any micromasking of the amorphous silicon by the surface oxides. Amorphous silicon etch rates on the 6 in. round samples were typically 4300-4500 Å/min with etch uniformities of ~12% (3s/average).
The processes were transferred to the 370 X 470 mm size, and amorphous silicon etch rates of ~3800 Å/min, with a uniformity of 15% (3s/average), were achieved using basically the same process chemistry. The RF power was scaled up to approximately match the power per substrate area.
Molybdenum etching
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| Fig. 1. SEM of a sloped molybdenum etch stopping on silicon nitride demonstrates high selectivity and very little grain structure. | ||||||||||||||||||||||||
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Fig. 2. Sophisticated dry etch techniques are required to
successfully fabricate modern FPD structures, such as this 1 mm
cathode well structure.
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Molybdenum is used in several layers of FED manufacturing, and the selectivity requirements for molybdenum etching can be demanding, depending on how the structure is fabricated. Additionally, molybdenum films are typically very rough because of its grain boundary structure and often give unacceptably rough etch profiles. 4
An SF6-based process was chosen as the most suitable chemistry to produce high etch rates and adequate selectivity to the photoresist mask. The refractory metals, molybdenum and tungsten, can be typically etched at high rates using a pure SF6 chemistry. 4 However, the proper choice of process pressure, RF bias power and additive gases is required to achieve the desired etch profile, roughness and selectivities to masking and underlying layers (Fig. 1). The etch trends for an SF6/O2/Cl2 chemistry are summarized in Table 1.
Molybdenum etch rates of up to 3200 Å/min were achieved for the main etch process. By controlling the etch parameters, a wide range of molybdenum:resist selectivities, from 0.27:1 to 2.7:1, were realized for affecting profile control.
Where high selectivity to the underlying layer is required, a slower etch rate chlorine-based chemistry is chosen for the overetch step. Etch rate selectivities greater than 20:1 are attainable for molybdenum to silicon, Si3N4 and oxide underlayers. Figure 1 shows a SEM from a sloped etch of molybdenum stopping on silicon nitride with high selectivity. The molybdenum etch rate exceeded 600 Å/min for the overetch process.
Oxide etching
The etching of the oxide insulating layer can be one of the most critical steps in the fabrication of FEDs, since the shape and critical dimensions of the contact-like etch of the oxide will impact the ultimate performance of the emitter tip. Etch rates of >3200 Å/min and a non-uniformity of ~10% (3s/average) were achieved for both 6 in. round and 370 X 470 mm samples using essentially the same CF4-based gas chemistry. Trends for the oxide etch process are shown in Table 2.
Minimizing the erosion of the photoresist mask during the oxide etch is essential, since the oxide etch requirements for FEDs can be in excess of 1 mm with aspect ratios greater than 1:1. For this CF4 -based gas chemistry, increasing bias power was found to increase the oxide etch rate, while maintaining the oxide to photoresist selectivity in the range of 0.8:1 to 1.2:1.
FED etch integration and manufacturability
Producing successful cathode well structures for FEDs relies on integrating several deposition and etch steps. 5 In this case, the formation of a cathode well structure was achieved by integrating the molybdenum etch process with the oxide etch process. Figure 2 shows the etch profile for the completed cathode well etch structure over a metal film.
Reactor chamber conditioning was found to be necessary to maintain stable results for the well etch process and other etch processes. Performance of the oxide etch process was tracked over ~40 substrates. In general, the oxide etch rates and uniformities were observed to be stable within the desired 15% (3s/average) control limits. Repeatability of the oxide etch rate and etch uniformity was monitored over a four-month period for the 370 X 470 mm substrate size. The variation in average oxide etch rate over this period was ~6.1% (3s/average). The TCP plasma technology was determined to be capable of meeting the dry etch requirements of manufacturing FEDs on 370 X 470 mm substrates.
Summary
Dry etch processes for the manufacturing of FED devices have been developed using a TCP source. Etch process results for the patterning of molybdenum, amorphous silicon and oxide films deposited on both 6 in. circular and 370 X 470 mm rectangular glass substrates have achieved high etching rates and good etch uniformities. The high-density low-pressure TCP source also provided methods for achieving the desired etch profiles for each of these steps, while maintaining the etch selectivity and low defect density.
Acknowledgements
Development of the Continuum FPD Etch System was partially funded by the
United States Display Consortium (USDC) under contract number RFP93-5.
The authors would like to thank John Watkins, Jesus Quijada, Kathy
Palmer and Denise Barrientos of Motorola and Les Saltzman of Lam
Research for their assistance in collection of the data.
References
1. P.H. Holloway, J. Sebastion, T. Trottier, H. Stuart, R. Peterson, Solid State Technology, August 1995, p. 47.
2. C.A. Spindt, Applied Physics, Vol. 39, No. 7, 1968, p. 3504.
3. A. Shih, A. Demos, R. Beer, Solid State Technology, May 1996, p. 71.
4. Y.J. Kuo, Electochemical Society, Vol. 137, No. 6, 1990, p. 1907.
5. U.S. Patent Document 5,055,077, Nov. 1991.
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Frank Mendoza has 14 years of experience
developing processes and process equipment for semiconductor and
flat panel display manufacturing. He is currently working for the
Flat Panel Display Division of Motorola and is responsible for
developing plasma etch processes for flat panel display
manufacturing. |
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Bill Sarette has 14 years of experience
working with sputtering, photolithography and plasma etching. He
is currently working in Motorola's process engineering group
developing processes and equipment for semiconductor and flat
panel display manufacturing. |
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Darrell McReynolds is a senior field process
engineer for Lam Research and is involved with the development of
the FED etch process using a TCP source. |
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Brett Richardson is a staff process engineer
in the Conductor Etch division at Lam Research. Richardson has
been involved with both the development of the TCP 9400
polysilicon etcher as well as the Continuum FPD etcher. |
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John Holland, PhD is the manager of the
Process R&D group within Lam's FPD division. He holds several
patents on the use of inductive sources for large area plasma
processing. |
