Experimental setup
Staff -- Semiconductor International, 6/1/1999
T hrough alignment sensitivity studies, design issues for new devices can be identified, impacting yield prior to release to full production. This case study on a low-yielding prototype HC11 J product, that yielded 10% to 20% lower than other qualified microcontrollers in the same device family, identifies the causes of device sensitivity to alignment at the control gate. Distinct types of CPU vector fallout were identified for misalignment in the X as well as Y direction. Further revision to this design was made to achieve the targeted yield for all qualified production devices.
For the prototype HC11 J product, the predominant failure at test probe
was the central processing unit (CPU). A distinct failure pattern was
seen on the wafers, which suggested a problem with alignment. A
commonality study was done on J device pilot lots that were processed
within a three-month period. Information collected in the commonality
study included reticles, steppers and CD measurements used. Particular
attention was placed on the active area and control gate because
alignment or dimension variation at these layers could result in CPU
fallout.
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| Fig. 1. Lens distortion between the Stepper A and B lenses. |
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| Fig. 2 . Matrix of forced misalignment, designated in each cell. Stepper A was used at the active gate layer, Stepper B at the control gate. |
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| Fig. 3. Alignment sensitive study forced misalignment in X and Y cordinates. |
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| Fig. 4. Varied off-shift in the X axis decreased yield and increased CPU fallout. |
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Fig. 5. CPU fallout results in constant Y off-shift and positive and negative X off-shift. |
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Fig. 6. At constant Y off-shift, yield is below target. |
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Since the commonality study showed a high frequency of repeat pattern failures, when particular reticles for the active area and the control gate layers were used, a reticle matrix lot was processed to eliminate the possibility of reticle interaction. Based on test probe data such as yield, CPU, SIDD, RAM FNC and ROM EPROM, 1 the experimental result showed that no reticle interaction was present between the reticles used at the active area and the control gate layers. Thus, the reticles were not the cause of the high CPU failure.
Additional information on the CDs and type of steppers used at all lithography operations were reviewed. Different steppers were used at the active area and control gate layers on both high- and low-yielding lots. Because different steppers have lenses with different radial distortion characteristics, marginal overlay errors can occur if different types of steppers are used at critical layers. 2 As shown in Figure 1,3 at a 4 mm radius from the center, a maximum lens distortion between the Stepper A lens and the Stepper B lens is evident at 0.04 and 0.1 mm, respectively, with the distortion vectors pointing in opposite directions: one negative and one positive. This means that alignment variation across the stepper field is largest (at 4 mm) when one layer is processed on Stepper B and the other on Stepper A. However, at an ~7 mm radius from the center, minimal distortion between the two types of stepper lenses is seen. As the mean shifts away from zero, the alignment on half the field will improve and get worse on the other half.
It was hypothesized that device J's yield problem was caused by alignment sensitivity because of design rule violations. Thus, additional experiments were set up to check the effect of misalignment on test probe parametric failure. Two experiments are described here.
Experimental setup
The alignment sensitivity study matrix was used to investigate the forced misalignment in both X and Y coordinates at the control gate layer, using Stepper A at the active and control gate operations. This would eliminate any Stepper A and Stepper B lens mismatch issues.
For the alignment sensitivity study on Stepper A to Stepper B, Stepper A was used to align the active area, and Stepper B was used to align the control gate with deliberate forced misalignment in the X and Y directions. This tested the hypothesis that device J's misalignment tolerance on Stepper A to Stepper A was different from Stepper A to Stepper B. The belief was that Stepper A to Stepper B lens distortion differences caused a higher sensitivity to misalignment.
The matrix setup for this study was the same as the prior study where groups of wafers were aligned within and outside of the lithographic specification limits. Figure 2 shows the experimental setup.
Data result and discussion
The effect of forced misalignment in both X and Y coordinates at the control gate layer, using Stepper A at the active and control gate layers, is shown on Figures 3 and 4.
The current process window for control gate alignment was ±0.3 mm for both X and Y off-shifts. The result in Figure 3 shows that with zero off-shift in X (0 mm) and Y off-shift ranging from 0.1 to 0.3 mm, targeted yields were achieved (targeted yield is set at a reference of 0%). However, a decrease in yield ranging from 14% to 53% from the targeted yield was evident when X had a constant off-shift of +0.3 mm. With minimal Y off-shift of 0.1 mm, the group already had a low yield of 33% from the target.
In Figure 4, with a constant off-shift in Y = 0.1 mm and varied off-shift in X from 0.3 to 0.3 mm, a decrease in yield and an increase in CPU fallout is evident for the 0.3 mm and 0.3 mm groups. Since the specification limit was ±0.3 mm, the result shown in Figures 3 and 4 proves that device J has an inherent sensitivity to off-shifts in the X coordinate. This sensitivity can be attributed to design flaws that made device J intolerable to slight misalignment at the control gate layer, which led to poor overlay of control gate to the active area. The large X and small Y steps in Stepper B's two-die cluster (2 3 3 = Y 3 X) step size explained the repeating CPU pattern failure at probe testing.
CPU fallout vector analysis
The type of CPU fallout on the wafers was analyzed by the amount of misalignments in both the X and the Y directions. This result is shown in Figure 5 with the following conclusions:
- With a large positive X off-shift (0.5 mm) and a large positive Y off-shift (0.5 mm), type "Q" CPU fallout will dominate.
- With a large positive X off-shift (0.5 mm) and some negative off-shift (0.3 mm), type "R" CPU fallout will dominate.
- With a large positive X off-shift (0.5 mm) and a slight positive Y off-shift (0.1 mm), a mix of type "Q" and type "R" CPU fallout will result.
- At constant Y off-shift (0.3 mm), and both positive and negative X off-shift (from 0.5 to 0.3 mm), only type "R" CPU fallout will result.
For the alignment sensitivity study on Stepper A to Stepper B, Stepper A was used at the active layer and a forced misalignment in the X and Y coordinates was done on the control gate using Stepper B. The result on this experiment is shown in Figures 6 and 7.
In Figure 6, at a constant Y off-shift of 0.07 mm, yields of 8% and 30% below target are evident on groups with X off-shift of 0.07 mm and 0.22 mm, respectively. Further decrease in yields for both groups are seen with more positive Y off-shift of 0.47 mm. This is unacceptable when compared with the on-target yield of wafers that were aligned using Stepper A at the active and the control gate layers. Again, this set of data verified device J's alignment sensitivity at the control gate when different steppers are used.
According to Figure 7, again at a Y off-shift of 0.07 mm, nominal yield of 8% from target was achieved when off-shift in X was 0.1 mm. and 0.16 mm. However, the yield dropped to 30% when X off-shift was at 0.22 mm, which was well within the alignment process window of ±0.3 mm.. Again, this showed that with a minimal amount of misalignment, yields were still 8% below target.
Conclusion
No reticle interaction was evident. The high CPU fallout was not caused by a repeating defect or registration error on the reticles; instead, it was due to device J's sensitivity to alignment.
Using Stepper A for alignment at the active and control gate layers forced misalignment at the control gate that caused CPU failures. This type of CPU failure is unique for off-shifts in the X and Y coordinates.
Using Stepper A for alignment at the active layer and Stepper B at the control gate layer forced misalignment at the control gate, which caused CPU failures. The CPU failures can occur at a much smaller misalignment (shift in X = 0.2 mm, Y = 0.1 mm), which proves that lens distortion characteristic between different stepper lenses resulted in a smaller process window.
It was found that device J requires alignment control tighter than the current process capability in order to produce yield at or greater than the targeted yield. To achieve this level of overlay control in the existing process, it is recommended that device J be restricted to one lens type during manufacturing. This requirement is not desired because it limits flexibility in a high- volume manufacturing facility. Thus, it would impact the manufacturability of device J in full production. A yield increase of up to 10% can be expected if the design error is corrected, lessening device J's sensitivity to alignment. A containment plan that calls for the use of Stepper A to align the active and control gates will be instituted until the design fix can be implemented.
This work has also proved that alignment sensitivity studies can uncover
design issues with new devices and predict its potential yield when
released for full production. Thus, it is recommended that this
methodology be adopted as part of new product qualification.
References
1. Motorola's M68HC11 Reference Manual, Prentice Hall Publishing, Copyright 1988, 1989.
2. S. Cox, D. Currier, K. Eskes, "Total mix and match overlay GCA Autosteps to GCA 8500, UT990's and UT 1500s," Proceedings from the Ultratech User's Meeting, May 13, 1996.
3. Distortion plot generated via Smart Set analysis software on ISI Autostep 200 steppers.
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The authors are with the Microcontroller Technologies Group, MOS 5 Die Manufacturing Group of Motorola (Mesa, Ariz.). Article inquiries should be directed to one of the following: |
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Su C. Chao |
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Kim Eskes |
