Investigating the Causes of CMP Micro-Scratches
Laura Peters, Senior Editor -- Semiconductor International, 6/1/1999
Researchers from UMC (Hsinchu, Taiwan) recently unveiled some of the critical parameters involved in the creation of micro-scratches during and after chemical mechanical polishing (CMP). The group determined that particle size distribution of the slurry most influences the evolution of micro-scratches, while wafer rotation speed and down force have minimal impact. Unsuitable rinsing and buffing steps following the main polish also contribute to micro-scratching, especially when hard polishing pads are used. The subsequent dilute-HF dip enhances the size and increases the number of micro-scratches, though post-CMP densification anneals can lessen micro-scratch severity. UMC's findings, summarized in the article "Investigation of CMP Micro-Scratch in the Fabrication of Sub-Quarter Micron VLSI Circuits," were presented at the 1999 CMP-MIC Conference in Santa Clara, Calif. in February.
Micro-scratch formation has long been a common problem in CMP processes, considered by some an inevitable result of mechanical polishing with abrasive slurries. In this study, UMC found that the probability of micro-scratching can be reduced by using slurries with particle size distributions in the 0.1 µm and smaller regime (Figs. 1 and 2). Another factor contributing to CMP damage is the buffing polish following the main polish. Buffing with soft pads reduces the likelihood of scratching over hard pads, although incorrect buffing produces worse results. HF dipping can increase the population of scratches or enlarge existing scratches. This effect is mitigated by adding a post-CMP densification anneal at 1000°C. Following oxide CMP, APCVD film annealing reduces HF wet etch rates from 1.1X to 0.96X, relative to pre-CMP densified oxide films.
UMC recommended optimization of CMP's subsequent rinsing and buffing steps
to minimize micro-scratch generation. However, slurry choice had the greatest
impact on the creation of micro-scratches. The effect of HF etching and enhancement
of micro-scratches was effectively mitigated by performing a post-CMP densification
to reduce wet etch rate. 
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Standard
for Static Charge in
Capital Equipment Now Available
Referred to as the Static Budget Guideline for Capital Equipment, SEMI's International Guideline E78-0098 sets criteria for developing a static budget for acceptable levels of charge in and around wafer processing and assembly equipment. Static charge causes electrical damage of integrated circuits on the wafer as well as equipment lockup (through microprocessor failure) of wafer processing tools.
The new guideline can be used to verify compliance of OEM tools with an equipment specification, while allowing tool manufacturers to better design equipment resistant to static charge effects and buildup. It provides a matrix of maximum recommended levels of static charge on products, reticles, carriers, minienvironments and input/exit ports of production equipment. For the first time, it defines types and test methods for ESD damage to semiconductor devices, while explaining methods of protecting processes from the costly effects of static charge. The guideline includes case histories for manufacturers of ESD-related equipment. One section describes grounding techniques, static dissipative materials and air ionization methods -- the most common means of controlling static in wafer fabs.
Ion Systems (Berkeley, Calif.) offers an equipment ionization program designed
to assist equipment manufacturers, minienvironment manufacturers and semiconductor
companies in complying with the Static Budget Guideline. Copies of the guideline,
formally known as "Electrostatic Compatibility: Guide to Assess and Control
Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment,"
SEMI Guideline E78-0098, are available at SEMI's website at www.semi.org.
