Manufacturing-Worthy Processes Merge DRAM and Logic Circuitry

T he merging of logic and memory components on a single chip poses special requirements in high performance technologies. At the IEDM Conference in December, NEC, IBM and other companies presented system-on-a-chip process flows designed to minimize the number of process steps. Engineers from NEC's ULSI Device Development Laboratories (Sagamihara, Kanagawa, Japan) reported on use of Ar⁺ and N⁺ implantation into gate oxides with dual-gate polysilicon doping using self-aligned thermal oxidation to produce a 20% gate oxide thickness difference between DRAM and logic regions without reducing reliability. Other engineers at NEC's Development Laboratories replaced conventional silicide and polysilicon-based structures of commodity DRAMs with shared tungsten structures. Tungsten acts as local interconnects and stacked contacts/vias in logic circuitry to realize a 40% to 65% reduction in interconnect resistance, while reducing process steps, thermal budget and surface step height for high manufacturability. Finally, engineers from IBM's Microelectronic Division (Hopewell Junction, N.Y.) merged a 0.617 µm² DRAM cell with a 4.2 µm² SRAM cell in a 0.18µm dual-damascene copper metalization process.

Fig. 1. Argon implantation enhances oxidation, while nitrogen implantation hinders it. (Source: NEC)

Fig. 2. The merged structure uses W/TiN/Ti plugs for substrate contact, damascene bilayer W metal-0 and bit line, bilayer W virtual via/plug, cylindrical bottom electrode and TiN/Ta2 O5/W capacitor. (Source: NEC)

Fig. 3. The process adds the trench capacitor module and four mask steps for the array to the pre-existing logic flow. (Source: IBM)

NEC's logic-embedded DRAM process implants Ar⁺ (5 x 10¹⁴ cm^-2) and N⁺ (5 x 10¹³ cm^-2) into the silicon substrate to form thicker and thinner oxides upon oxidation. Ellipsometers and C-V measurements determine oxide thickness (Fig. 1). After polysilicon and Si₃N₄ deposition, P⁺ implantation and removal of nitride in the NMOSFET region forms a nitride cap on PMOSFET devices. An oxide mask allows B⁺ implantation of the PMOSFET region, while nitrogen recoils from the nitride cap, suppressing flatband voltage shifts induced by annealing. Oxide mask and nitride cap are removed; metal is deposited; gate electrodes are patterned, and transistors and capacitors are fabricated.

NEC's merged DRAM structure (Fig. 2) shares tungsten-based damascene bit lines, storage capacitors and contact plugs in DRAM memory cells with local interconnect lines and stacked contacts/vias in the device's logic portion. Bilayer tungsten is compatible with Ta₂O₅ dielectric full-metal capacitors. Commodity DRAMs use doped polysilicon with high-temperature activation, an incompatible process with back-end multilevel metalization. NEC's process uses cobalt-salicide technology; contacts to the substrate are opened and implanted/activated where necessary; then only low-temperature processes are used for transistor, salicide and Ta₂O₅ integrity. Bit-line/metal zero is formed by etching a line trench down to and through a thin nitride-based etch stopper to a conventional W/TiN/Ti-based contact plug. A thick PVD/CVD W bilayer fills the trench, followed by etch-back or CMP. Capacitor bottom electrode and contact-hole plug are formed on the corresponding contact plug using bilayer W. Cylindrically-shaped bottom electrode uses W-CVD. By partially or completely removing surrounding frame oxide with a mask to prevent logic-block oxide erosion, electrode surface area is increased. A 10-12 nm Ta₂O ₅ layer with UV/ozone treatment and TiN top electrode are deposited, masked and etched. The top electrode and dielectric are removed, and the bottom electrode is exposed to serve as a virtual via down to M₀ . Via an M₁ logic process steps follow.

IBM's embedded DRAM design featured the highest reported device performance for a 1.54V bulk silicon technology, with a fixable retention time of >256 msec at 85°C without degradation in logic device performance or density. The 0.617 µm² DRAM cell uses buried strap trench capacitor technology, characterized by excellent planarity, reduced cell density penalty without self-aligned diffusion contacts and elimination of additional middle-of-the-line heat cycles. The array cell has a bordered bit-line contact. Bit-lines use a damascene copper process; word-lines are strapped with the second damascene copper level. The process flow (Fig. 3) adds the trench capacitor module and four mask levels of the array device to the base 0.18 µm process. On non-epi wafers, an arsenic plate is formed by out-diffusion from a recessed arsenic-doped glass, not required if epi wafers are used. Three poly deposition and etch steps define the collar oxide region; the buried strap and oxide cap on which the passing word-line crosses; the node capacitor is 74 Å oxide equivalent. The DRAM array polysilicon is pre-doped, because deep source/drain implants are blocked from the node junction and only implanted into the bit-line contact side of the array device.