IMEC Finalizes 0.35 µm BiCMOS Integration
Staff -- Semiconductor International, 4/1/1999
The Inter-University
Microelectronics Centre (IMEC, Leuven, Belgium) has developed an epitaxial base
technology for BiCMOS devices. This technology is based on a selective silicon
epitaxial growth process that is compatible with a double polysilicon inside
spacer architecture for the emitter-base formation as a precursor to a SiGe
technology. The resulting structure (Fig. 1) has very low device parasitics,
excellent ideality of its base current, a current gain of more than 80 and high
breakdown voltages.
This process starts with a conventional arsenic buried layer isolation, collector epitaxy and active area definition. Collector sinker regions are implanted and diffused; followed by the CMOS well ion implants and anneals. Before the gate oxide is grown, a 100 nm thick TEOS layer is deposited and selectively etched in the CMOS regions. Then comes gate oxidation and polysilicon deposition. This poly layer serves as the CMOS gate material and the poly base leads. A 200 nm thick nitride layer is deposited and sequentially dry etching the nitride and the poly layer opens the base region. A thin nitride spacer seals off the poly sidewall. The TEOS is wet etched, which results in a lateral undercut. The 45 nm thick epitaxial base is grown selectively at 800° C with a boron doping concentration of 5 x 1018 per cm3 at a pressure of 40 Torr. The processing then continues as in a classic double poly inside spacer process flow.
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| Fig. 1. This image shows a cross section of the epitaxial base bipolar transistor. (Source: IMEC) |
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Fig. 2. These high frequency characteristics show an FT value of 24 GHz and a maximum oscillation frequency of 50 GHz. (Source: IMEC) |
Epitaxial base technology can combine good analog performance, such as low base resistance and high early voltage, with high-speed performance to yield a very attractive technology for high-frequency products (Fig. 2). The process can produce devices with transition frequencies of 24 GHz and early voltages of 30 V. The reduction of device parasitics results in maximum oscillation frequencies of 50 GHz.
The growth of the selective epitaxial base must result in a good link up with the poly base leads. IMEC has achieved this by optimization of the dielectric stack and the growth conditions," stated Dr. Stefan Decoutere, IMEC's group leader for mixed signal technologies.
This year IMEC intends to develop modules in 0.25 µm BiCMOS with double poly architecture and effective emitter widths of 0.2 µm. On-chip spiral inductors will be fabricated in thick metal and 2.5 µm aluminum. In situ arsenic doped poly-emitters will be used to reduce two-dimensional emitter out-diffusion effects for scaled double poly architectures, while isolated CMOS will be used for the reduction of digital substrate noise. Work on 0.18 µm circuits will follow later.
