GaAs ICs: The Future Has Arrived
Staff -- Semiconductor International, 4/1/1999
 By leveraging off Si processes, H-GaAs processing provides an economical approach to GaAs fabrication.  |
Today, the future has arrived.
GaAs ICs provide the high performance required by multiple layers of optical fiber communication systems. Currently, by increasing the speed in each transmission channel on a single fiber utilizing wavelength division multiplexing (WDM), the need for 5X increase in system bandwidth is being addressed. However, the data rates of these systems, mainly 2.5 Gb/s (OC-48/STM-16), are beyond the capability of conventional silicon CMOS technology but are a natural application for the performance and cost effectiveness of GaAs ICs. Additional trends in new memory standards such as RAMBUS have created new applications that require the performance of GaAs ICs within the automatic test equipment (ATE) marketplace.
Where GaAs differs
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The first 6 in. GaAs fab is located in Colorado Springs, Colo., and uses the H-GaAs process for IC manufacturing. |
- GaAs wafers are very brittle and often require modification to equipment to prevent breakage;
- GaAs has no useful native oxides, whereas Si easily oxidizes to create high-quality SiO2 films that can be used for gate oxide and isolation;
- Arsenic dissociates from the GaAs substrate at relatively low temperatures (>500°C), whereas Si is very stable at >1100°C, and
- GaAs wafers have only recently become available in 6 in. diameters as compared to the 8-12 in. diameters in Si.
| Table 1. COMPARISON OF FABRICATION PROCESSES | |||
| H-GaAs | Traditional GaAs | Silicon | |
| Semiconductor | compound | compound | single crystal |
| Electron mobility (cm2/V-sec) | 8500 | 8500 | 1500 |
| Bandgap (eV) | 1.424 | 1.424 | 1.1 |
| Fragility | brittle | brittle | n/a |
| Wafer size (in.) | 4, 6 | 4 | 6 to 12 |
| VLSI circuits | yes | no | yes |
| Thermal stability >500° C |
As dissociates | As dissociates | n/a |
| Thermal oxidation | poor | poor | excellent |
| Gate lengths for equivalent performance | 0.5 µm | 0.35 µm | 0.35 µm |
| Al etched interconnects | yes | no | yes |
| Standard Si equipment | yes | not always | yes |
| Transistor | MESFET | MESFET | CMOS/Bipolar |
| Gate | Tungsten | Ti/Pt/Au | polysilicon |
Today, GaAs ICs represents <5% of the total IC market; of that, ~70% are for digital applications and 30% for analog. However, in the high-speed market (>1.2 Gb/s), GaAs ICs play a dominant role, claiming over 70% of the business.
GaAs production
In the mid 1980s, several companies believed in the potential of GaAs ICs, and by the early 1990s, technology had been developed to make commercial ICs a reality. Some used the traditional process developed in the aerospace industry. However, to address particular technology and cost issues, Vitesse Semiconductor developed a proprietary process called high-integration GaAs (H-GaAs), which incorporated standard silicon processing techniques to the manufacture of GaAs VLSI products. Properties of each process, silicon, traditional GaAs and H-GaAs are shown in Table 1.
H-GaAs, high-integration GaAs manufacturing technology, developed in the mid-'80s, is based on proven silicon MOS manufacturing methods in use at the time. However, there were challenges that needed to be overcome. The goal was to create robust, high-speed FETs with multilevel aluminum interconnects that operate at low power and are competitive with bipolar, biCMOS and traditional GaAs technologies. Each of these 'mainstay' processes poses particular challenges. For example, Si bipolar technology is confronted with manufacturing complexity, large die size and high power.
Traditional GaAs processes are unable to achieve large-scale circuit integration due to the requirement for gold-based gates, contacts and interconnects, and restrictions in circuit layout due to the FET orientation and does not allow for interconnect metal over gates. For example, the FET layout orientation is typically limited to one direction, whereas in H-GaAs, the FET is laid out in two directions, facilitating better packing density. In addition, traditional GaAs does not allow interconnect metals to pass over the FET, thus limiting the complexity of the chip. Instead, it requires techniques such as liftoff or ion mill to define the metal levels, which do not lend themselves to VLSI manufacturing.
Si vs. GaAs processing
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Fig. 1. Unlike traditional GaAs processing, a typical MESFET structure using H-GaAs allows for more layers and device complexity. |
GaAs active areas and field oxide isolation layers are defined in a similar way to standard Si MOS processing except that all dielectrics are deposited on GaAs with low-temperature (<480°C) PECVD rather than thermally grown oxides. Both enhancement and depletion n-channel MESFETs can be created by simply controlling the amount of n-type dopant implanted into the active areas. Typically, silicon atoms are used as the n-type dopant for GaAs. The actual percentage of n-type activation is dependent on a number of parameters, in particular the anneal process, capping layer and film stress. In Si processing, phosphorus and arsenic are typically used as n-type dopants and act only as donor impurities.
H-GaAs processing
The gate of a MESFET is a refractory metal (tungsten); it is relatively easy to define and etch 0.5 µm gate lengths. This provides a reliable, stable Schottky diode and MESFET. To optimize FET performance, unlike traditional GaAs processing, H-GaAs uses a self-aligned gate method in a similar manner to MOSFET processing. The key requirement is to achieve a low source-drain resistivity while maintaining a high gate-drain breakdown voltage. This is done by lightly doping the source/drain region n-type, followed by a deposition and etchback process to create a dielectric 'spacer'' along the edge of the gate. The spacer effectively confines the heavy N+ implant to ensure that doping next to the gate edge is kept light, providing higher breakdown voltages. Since the rest of the open active areas receives the N+ implant, the contact resistance is low.
One key difference between GaAs and Si processing is a special capping dielectric layer required to prevent arsenic dissociating from the substrate during thermal anneals. Traditional GaAs has used silicon nitride (sputtered, PECVD) and silicon oxynitride (PECVD). H-GaAs uses a PECVD silicon nitride film that has been optimized to control stress, index and thickness. Without this film, the FET would essentially be destroyed. The H-GaAs approach has demonstrated cleaner deposition and easier control.
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Fig. 2. The use of H-GaAs allows for integration of multiple functions onto a single chip, surpassing that of traditional GaAs processing. |
Following the single deposition contact layer, the basic H-GaAs MESFET process is complete and the wafer is ready for the interconnect process. Traditional GaAs is limited to less complex structures with only two metal layers and therefore lacks the functionality of devices processed using the H-GaAs approach, which can have up to four metal layers. For example, using the H-GaAs process, a 16-bit multiplexer with clock generator and laser driver can be incorporated onto a single chip (Fig. 2). On the other hand, with traditional GaAs processing, each function would be processed on a separate chip. The total number of layers using the H-GaAs process is 13-15. CMOS typically requires ~17 layers. In comparison, traditional GaAs is limited to nine to 11 layers.
H-GaAs interconnects
H-GaAs interconnect formation uses standard PECVD oxide films and spin on glass (SOG) planarization to provide low capacitance insulation between interconnecting aluminum-based metal lines with refractory metal barriers. This is similar to Si processing of the late '80s. Surprising is the amount of relatively old process techniques used to fabricate such high-performance devices. This is a reflection on the inherent advantages of H-GaAs and helps keep the process relatively simple and cost effective.
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Fig. 3. A 32-bit parallel to serial backplane transceiver with data rates of 2.6 Gb/s is an example of the integration capability of the H-GaAs process. |
Summary
The H-GaAs process has produced GaAs IC's that operate at 2.5 Gb/s and 10 Gb/s, whereas traditional CMOS technology provides switching element ICs with data rates of 100-200 Mb/s. The demand for more bandwidth will continue with the growth of data and telecommunication needs.
H-GaAs solved two major problems that had prevented GaAs ICs from receiving wide acceptance: improved process complexity and reduced cost. Today, the H-GaAs process is used to manufacture VLSI products that have a million transistors, embedded memory, transducers and detectors, all at competitive pricing to silicon products. GaAs ICs have reached the point where 'light to CMOS' fiber communication solutions are available and truly integrated circuits with optoelectronics, digital and analog circuits all on the same substrate (Fig. 3) are a reality.
For the past five years, H-GaAs production growth has exceeded 60% per year. Today, with the recent availability of 6 in. wafers, the world's first commercial 6 in. GaAs production facility has come on line, the Pierre Lamond Wafer Fabrication Facility in Colorado Springs, Colo. (lead photo). The cleanroom is a 15,000 ft2 ballroom design with a sub-fab. The relatively small size provides many cost savings, because standard off-the-shelf facility equipment are used. In addition, blowers are located on the side of the fab rather than over the ceiling, resulting in significantly quieter operation. From ground breaking to first yielding production wafers was 15 months. For the transition from 4 to 6 in. wafers, the H-GaAs process scaled relatively easily. Together with the advanced equipment set, a considerable cost advantage over bipolar processes such as Emitter coupled Logic (ECL), traditional GaAs and Si-Ge have been realized.
