Choices and Challenges for Shallow Trench Isolation

Laura Peters, Senior Editor -- Semiconductor International, 4/1/1999

Relative to its LOCOS predecessor, STI achieves better scaling and isolation between transistors at the expense of process complexity.

From a design standpoint, the transition from LOCOS to shallow trench isolation (STI) is a natural. STI significantly shrinks the area needed to isolate transistors while offering superior latch-up immunity, smaller channel-width encroachment and better planarity. From a processing point of view, however, the transition to STI is a little more complicated. The greatest challenges lie in providing void-free, seamless gapfill by CVD and uniform planarization by CMP.

Engineers use reverse masks, dummy structures and other techniques to ensure uniform planarity, with single-step CMP as the ultimate goal. This article reviews recent progress in creating STI structures, highlighting differences among various gapfill techniques and CMP tool, consumable and operational choices that optimize STI results.

Device Issues

In-situ STI etch using non-depositing chemistry enables enhanced corner rounding profiles and eliminates the need for frequent chamber cleans. (Source: Applied Materials)

DRAM devices inherently require a more robust isolation region as sensitivity to even the smallest amount of leakage causes retention time failures in the memory cells. 'Your isolation technology now has a lot of influence on your transistor characteristics, which you did not have before with LOCOS,' said Ludo DeFerm, associate vice president of Silicon Technology and Device Integration for IMEC (Leuven, Belgium). DeFerm explained that dummy features cannot be used for analog and mixed signal devices 'because you have coupling capacitance and additional noise affecting analog devices that you don't have with digital.' The STI process is designed with device needs in mind, but also process capability. Dr. Robert Soave, marketing manager of diffusion/CVD systems at TEL (Austin, Texas), added, 'The big three issues with STI are integration, integration, integration. Getting a good fill does not mean you have a good STI process, it's the whole process module that matters.'

The STI Process

The most basic STI process includes silicon etch, oxidation, trench fill by CVD and CMP. With scaling beyond 0.25 µm, today's more elaborate process (Fig. 1) typically begins with deposition of a pad oxide and a nitride layer (used as a polish stop), followed by etching of the dielectrics, then the silicon. After trench etch, a liner oxide is grown and the trench is filled by CVD. The oxide may be annealed for densification, and then the structure is planarized by CMP. Next, the nitride and pad oxide layers are removed by wet etch; a thin, sacrificial oxide layer is grown (to anneal damage to the silicon surface), followed by another wet etch. The gate oxide is grown, poly deposited and gate patterned, leading to subsequent front-end processes.

Fig. 2. To address dishing (a), engineers use a reverse mask (b) dummy active area (c) or additional nitride layer (d).

During CMP, the oxide layer polishes faster than the nitride stop layer, causing 'dishing.' Engineers most commonly address planarity issues using reverse masks, followed by dummy active areas and a newer, nitride cap approach (Fig. 2). However, the goal is to eliminate any additional masking layers or process steps. 'We're trying to maximize planarization capability while minimizing design alterations,' said Greg Amico, 200 mm global product manager of CMP at Applied Materials Inc. (Santa Clara, Calif.). 'The holy grail is if we could have such a good CMP process that the designers wouldn't have to modify the process much - we believe we're very close to reaching that point.'

Trench Etch

Profile and angle control are the primary issues in STI etch. 'Angle is one of the most varied parameter specifications we receive - from angles of 70° to 88°,' said Dragan Podlesnik, Applied Materials deputy general manager for silicon etch. He added that some customers even request two-slope profiles, 'driven by their filling technique and specifications on the filling process.'

Though influenced little by the actual etch process, another key to STI is corner rounding, generally accomplished by growing a thin thermal oxide layer in the trench. The top trench corner represents an abrupt transition from the transistor active area to isolation. If the polysilicon gate is able to wrap-around into the isolation corner, a parasitic conduction path in the sub-threshold regime occurs, causing a 'double hump' in the I-V curve (Fig. 3). The reverse narrow channel effect is more severe if the trench oxide recesses below the surface of the silicon (Fig. 4). A pad oxide undercut following trench etch, together with a high-quality oxidation process, nullifies this effect.

Fig. 3. Gate wraparound into the isolation corner causes parasitic corner capacitance and the characteristic 'double hump' in the curve.

Fig. 4. Corner rounding helps eliminate the reverse narrow channel effect that causes sub-threshold leakage. Recess of the isolation region below the silicon surface exacerbates the problem.

Engineers at TI recently found corner rounding is enhanced by adding HCl to the dry O₂ ambient during oxidation, by raising the oxidation temperature (RTO), by implementing Mini LOCOS oxidation before trench etch, or by re-oxidizing the trench oxide in dry O₂ at high temperatures (1100°C) after CMP.¹ Importantly, the last two approaches reduce active area. Regardless of growth conditions, the oxidation layer enhances corner rounding, successfully anneals any damage from the plasma etch, helps control leakage and provides a good interface for the deposited oxide. Figure 5 shows an 87° trench with corner rounding and oxide/nitride layers on top.

Beyond profile control and corner rounding, Podlesnik expects future STI performance to rely on CD control. 'Currently, the main battleground for CD control is in gate etch, but we are seeing this is going to be important for STI, especially if we are doing in situ mask open.' In situ hard mask open and silicon etch greatly enhances productivity by etching the nitride, pad oxide and silicon trench in the same chamber. This process is offered by Applied Materials, Lam Research Corp. (Fremont, Calif.), TEL (Austin, Texas) and other etch tool manufacturers. Selectivity to photoresist, according to Podlesnik, is one of the challenges for in situ mask open. Lam Research's Greg Campbell, VP and general manager of the Etch Product Group, stated, 'Through production implementation of in situ hardmask open, our customers have realized certain benefits like easier corner rounding by controlling the taper of the hardmassssssssk and fewer microloading issues.' Corner rounding at the base of the trench, adjusted by varying etch parameters, minimizes stress to the silicon lattice upon oxide fill.

Further concerns include depth uniformity and stability of depth addressed through the stability of chamber conditions. 'With different patterns, structures, open areas, different microloading, you affect your etch rate, so that means you have to recalibrate the depth,' Podlesnik explained. He added that there is great opportunity for a production-worthy endpoint system for trench etch.

Fig. 5. Etch profile of 87° shows top corner rounding and bottom corner rounding. (Source: Lam Research Corp.)

'Given STI is an isolated technology, concerns over metallic contamination increase with shrinking device dimensions,' explained Campbell. To address this issue, Lam replaced all ceramic chamber components with quartz. Etch productivity is also strongly affected by chamber cleaning frequency. Lam addressed particle issues by introducing a Waferless Autoclean plasma process that cleans the chamber and electrostatic chuck. Applied Materials implements Clean Chemistry STI using fluorine throughout the etch, which eliminates the need for frequent dry cleans.

Oxide Fill Choices

The most important performance criterion for STI oxide fill is gapfill extendibility. In shallow trench fill and interlevel dielectric (ILD) gapfill, CVD tools are pushed to their limits. Fortunately, the transition to copper damascene structures eliminates the gapfill requirement for ILD, freeing some of the tools for STI. Table 1 summarizes fill characteristics for three deposition materials.

Table 1. Comparison of Gapfill Oxides
		Oxides
Criteria	Concerns	HDP	SACVD (TEOS-O3)	TEOS-O3
Void-free gapfill Trench width/depth	Weak seam poly-wrap-around	0.16/0.5	0.21/0.5	0.13/0.3
Densification	Etch rate reduction	No	Yes	Yes
Shrinkage	Stress/defects	0%-0.8%	5%-6%	<5%
Process steps	Throughput	1 step	seed/cap	2-step
Step height uniformity	STI comer Gate oxide reliability	good	poor	good
(Source: Texas Instruments)

Today's requirement to fill 2:1 aspect ratio, 0.20 µm wide trench, with 85° profile angle, is met by APCVD (ozone/TEOS), LPCVD TEOS, SACVD or HDP CVD tools. Tube furnace processes became especially popular in early STI application due to the very low metallic contamination levels required for isolation technology. Techniques such as HDP-CVD were not initially used due to aluminum contamination issues.

Since then, HDP has become a mainstream technology and tool manufacturers control aluminum contamination below 5 x 10¹⁰ atoms/cm², the current specification. 'We've already demonstrated gapfill to 5:1 aspect ratio for 0.10 micron spaces, so there's quite a bit of margin in the process for future generations,' said Dana Tribula, director of HDP-CVD at Applied. Applied's Remote Chamber Clean technology uses an upstream plasma, 'so that only free fluorine enters the chamber during cleaning.' Since the chemistry does not attack aluminum of ceramic chamber components, it significantly lowers matallic contamination levels. 'As an additional benefit, the remote plasma clean operates in a regime where you don't emit any perfluorocarbons,' explained Tribula.

LPTEOS gapfill depends on the rapid removal of byproducts from high aspect ratio trenches. Soave explained, 'Because the byproducts cannot diffuse out of the trench, the oxide film at the top of the trench grows faster than at the bottom and you get voids,' Soave said. 'For 0.18 µm processes, we adjust the process parameters to minimize byproduct inhibition, and use a slightly different chemistry to prevent voids and get a uniform deposition rate.'

APCVD tools from Watkins-Johnson (Scotts Valley, Calif.) and Canon/Quester Technology (Fremont, Calif.) had many early wins in STI and the companies assert the extension of their technology to 0.18 µm and beyond. 'We're filling 0.07 µm structures with 6:1 aspect ratio and 88° profiles,' said Tom Pye, manager of strategic planning for Watkins-Johnson. APCVD may also allow different deposition thickness on nitride and oxide,² possibly simplifying its integration with CMP.

DRAM devices are rapidly driving trench aspect ratios to 5:1 due to a thicker oxidation layer requirement to control leakage. This jump in capability is causing many companies to change gapfill chemistry and processes to fill the gaps. For instance, a year ago Novellus (San Jose) introduced an HDP tool upgrade that enables directional deposition. 'Surprisingly, by reducing the amount of sputter etch you need in the process, we can extend gapfilling capability from 3:1 aspect ratio to 5:1,' explained Drs. Wilbert van den Hoek, group VP of dielectrics for Novellus Systems Inc. 'We've eliminated argon from the process, so the oxygen takes over as the sputter etch agent.' Over the next six months, Novellus will introduce a new gas injection technology that promises to dramatically increase silane utilization in HDP.

Fig. 6. High aspect ratio (5:1) STI structures 0.15 µm wide are filled with HDP deposited oxide. (Source: IBM)

Beyond gapfill, the oxide must deposit seamlessly and be dense enough to endure CMP and subsequent wet etch steps. For this reason, post-deposition annealing, even for HDP films, is common. 'If the deposited oxide isn't of similar quality to thermal oxide, when you remove 50 Å of thermal oxide you could remove 200-300 Å of your trench oxide that you worked so hard to put in place,' said van den Hoek.

CMP Optimization

Process margin for STI CMP is small due to high pattern dependency and low oxide to nitride selectivity that causes dishing. The CMP step must remove all the oxide from the active area, without eroding too much of the nitride layer (typically 300Å of the 1600Å beginning thickness is good). Since all CVD methods demonstrate some pattern sensitivity, the CMP process must be optimized for the fill process. For instance, APCVD's profile is very different from HDP's characteristic 45° triangles (Fig. 6). Following CMP, nitride and pad oxide wet etch steps are isotropic. Therefore, the thinner the oxide and nitride layers, the better.

The nitride polish stop layer is typically deposited by LPCVD. Novellus offers an alternative HDP-CVD nitride process that is indistinguishable in composition from LPCVD nitride but allows control of film stress. 'Another integration advantage is the film is grown only on the front of the wafer, eliminating a backside removal step,' van den Hoek said.

Fig. 7. Evolution of oxide thickness on active areas (colored lines) and thickness variation (black line) with different pattern density (left), compared to oxide thickness on trench areas (right).

Trench polish quality is measured by within-wafer uniformity, wafer-to-wafer uniformity, control of trench oxide thickness and range, remaining nitride thickness and range, and defect levels within-wafer and wafer-to-wafer. At 0.18 µm, most semiconductor manufacturers are working toward direct-polish solutions, eliminating reverse masks and other methods, putting all the burden for planarity on the CMP tool, slurry and process. According to Willy Krusell, VP and general manager of the CMP and Clean Business Unit at Lam Research, some companies never considered another approach. 'I've heard a fab can save upwards of $100 million a year by going to direct polish,' Krusell said. Interestingly, the challenges in STI polish are similar to those in copper polishing, especially regarding dishing. 'If you can do a really good direct polish on STI, you can probably do a good dual damascene copper polish,' observed Krusell. The most difficult challenge is to even out the pattern dependence of oxide thickness over active areas and trench areas (Fig. 7).³ Because of the more regular pattern density on DRAM devices, they tend to have more manageable STI CMP processes than logic devices.

A recent study by Applied Materials showed that pad hardness, head/platen speed and not polishing velocity, as was claimed by some, has a dramatic impact on planarity.⁴ Contrary to general perceptions, the company also found that high selective slurry can have a negative impact on dishing. 'With high selective slurry, we found more dishing and some rounding of the nitride corners. We attained better results with a low selectivity slurry, an efficient endpoint technology, a harder polishing pad and an optimized process in general,' said Amico.

Cost of consumables in STI CMP depends on pad lifetime, frequency of pad conditioning, in situ versus ex situ conditioning, slurry costs, efficiency of cleaning process and many other factors. 'Leading-edge DRAM makers who do the most aggresive shrinks have lowered cost of consumables to around $2 a wafer, driven by intense cost and pressures,' Krusell said.

References

1. M. Nandakumar, et.al., 'Shallow Trench Isolation for Advanced ULSI CMOS Technologies,' 1998 IEDM Tech.
2. T. Curtis, et.al., 'APCVD TEOS Ozone Thin Film Integration for Multilevel Interconnect Process Modules,' VMIC, June 1994.
3. F. Chen, et.al., 'Theoretical & Experimental Study of Post-CMP Thickness Variation on STI Structures with HDP Oxide Gap-fill,' VMIC, June 1998, p.481.
4. R. Jin, et.al., 'A Production - Proven Shallow Trench Isolation Solution Using Novel CMP Concepts,' CMP-MIC, February 1999, p. 314

Talkback

We would love your feedback!

Post a comment

» VIEW ALL TALKBACK THREADS

Related Content

• Topics
• Author

Related Content

 

By This Author

• Ziptronix, Raytheon Prove 3-D Integration of 0.5 µm CMOS Device
• 300 mm Fabs Need to be More Competitive
• High-k/Metal Gate Announcements ?
• Strained Silicon: Essential for 45 nm
• Haze Defects Are a Solvable Problem (Part 2)
• » MORE

SPONSORED LINKS