Copper Electroplating Enters Mainstream Processing
Alexander E. Braun, Associate Editor -- Semiconductor International, 4/1/1999
 The three drivers moving the industry to copper: performance, lower power requirements and cost have intensified, and it is no longer a matter of if, but when.  |
The question shifted from whether we should use copper to how to deposit and process it. The early adopters already had decided that electrolytic deposition, a plating process, was the preferred method. However, the bulk of the industry still wondered whether a sputtering-type process with a reflow or a CVD process would ultimately be best.
Press releases from IBM, Motorola, SEMATECH, and AMD during the latter part of 1997 proved electroplating had compelling advantages as a deposition technique when applied to very high-aspect-ratio features that are part and parcel of the damascene process, one of the enablers for the use of copper. In June 1998, Novellus, working with a process developed by IBM, introduced the first production-worthy copper deposition system.
So the industry concluded that, yes, copper would be used and that plating was how it would be deposited.
Electroplating Ramps Up
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The CVS analysis technique has been long used for on-line monitoring and control of additives. It is better than lab instruments due to better environmental control and the absence of the human factor. (Applied Materials) |
A year ago, according to Taylor, the question in the minds of semiconductor manufacturers was whether manufacturing-worthy tool sets were available. 'The industry wanted a stand-alone deposition system with the requisite reliability and appropriate throughput to take the step to high-volume manufacturing. We'd been working with pilot line prototyping facilities, but the question was whether it was scalable. Now we know the answer is a resounding 'Yes!'' He added that there are now other systems, besides Semitool's, specifically designed and configured for high-volume manufacturing.
Admittedly, hardware is still the focus - the plating tool itself. However, the horizon has broadened to include support infrastructures necessary to support multiple installations of these tools in high-volume manufacturing environments.
According to Taylor, issues being addressed today include questions such as, 'How do we support 10 or more of these plating systems running in a common facility using a chemistry different in terms of process control from what the industry has previously experienced? What are the logistics of supplying consumables to these tools, exhausting spent chemistry, doing on-line analysis and chemical composition control for long-term stable operation?'
Over the next year, process control will be a major development focus for equipment suppliers and the industry. 'Coming up the maturity curve for electroplating on ULSI devices, performing rigorous analyses of the chemistry and how its composition changes with time as a consequence of plating and taking the appropriate measures to counteract these changes will be fundamental,' Taylor said. 'Real-time analysis and feedback control of electrolyte composition are central to the transition to high-volume manufacturing.'
For the metal deposition end of the process, control of the chemistry will be key, whether it is controlling the plating chemistry composition, or the way the chemistry is introduced into the reactor, or the integration of multiple wet-chemical processes before or after the metal deposition step. For example, the ability to carry out processes whereby the backside of a wafer is cleaned or the device side is treated with an appropriate chemistry following deposition is becoming crucial.
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Fig. 1. Copper interconnect, showing a cross-section of a six-level dual inlaid copper. The polysilicon has been etched away to expose all of the metal layers. (Source: Motorola) |
Taylor is the first to admit that although Semitool maintains a leadership position as a supplier of electroplating capability, there are still challenges to be faced. 'One is the process engineer's unfamiliarity with a wet process for metal deposition. The disciplines employed for bulk chemical delivery to wet stations aren't that new, but it's only been in the last two years that bulk CMP slurry supply, for instance, has been widespread. We're going to see the same evolution of electroplating chemistry handling and delivery and maintenance methods.'
Managing the Electrolyte
Applied Materials (Santa Clara, Calif.) states it has a solution that solves the industry's concerns about copper electroplating. Daniel Carl, general manager, Copper Division at Applied's Metal Deposition Product Business Group, defined the problem succinctly. 'As we go to high-aspect ratios, electrolyte management increases in importance. Presently, for advanced applications, we're using precise feedback control of additives to maintain filling properties as well as tailor the film's initial grain size and brightness or roughness.'
The additives come in many categories, the most critical of which are inhibitors and accelerants. Inhibitors remain on the wafer surface, reducing the copper deposition rate on planar surfaces. Accelerants speed or enhance deposition in the feature size of a via or a trench, for example. When these are balanced, it is possible to get a correct fill of a high-aspect ratio structure without voids and seams. However, high precision is required to balance these materials; furthermore, a brightener might be used for final surface finish and roughness as it integrates with CMP. 'Electroplating's Holy Grail is continuing, in-situ analysis and feedback electrolyte control right on the system,' Carl said. 'Fabs cannot afford to take a sample, send it to an analytical lab and get a result 12 hours later.'
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Fig. 2. The Electra Copper Deposition System has an onboard, closed-loop electrolyte management system, which determines when additives need dosing. Shown here is a copper barrier and seed. The via critical dimension is 0.22 µm; its depth is 1.25 µm. (Source: Applied Materials) |
The system has a 200 , tank with filtration on board and six dosing channels. This is combined with an in-situ measurement ability integrated with the chemical cabinet and system software, to perform on-line measurement. 'Let's say, for example, that the system monitors that inhibitor x is under concentration,' Carl said. 'It immediately calculates how much is needed to dose the tank and does it,' he said. 'Feedback is on the order of minutes rather than hours.' He added that the system removes the uncertainty element from processing, putting it under standard control and controlling it actively instead of passively.
The Applied electroplating system has the capacity for three twin electroplating cells - three sets of two cells - served by a central wet robot that moves two wafers at once. The cells are balanced by a two-cell spinner/drier. The system's wet portion is separate from the dry portion. The front end has a robot servicing a cassette and orienter that places wafers on a dry stand above the spinner/drier, with a shield in the middle. The front end only handles dry wafers, while the back end is devoted to wet surfaces.
Wafers go in, move to the electroplating cell, then to a spinner/drier and out. The architecture is designed to handle over 60 wph, and will fit 300 mm wafers in the same footprint.
In the same spin rinse dryer, the wafer is loaded above the hood height and dropped into a cavity with three chemical channels below and three above the wafer. While the wafer is rotated, a chemical is introduced to remove any backside copper, then DI water is sprayed on the front side. By balancing the flows, it is possible to control how much material from the backside overwraps, either on the side or the bevel, or just above the bevel, or whether it is kept from coming to the front side at all. At the end, the copper surface can be passivated after it has been cleaned by the DI.
Additive control is only one aspect of the system. 'What we're controlling is a proprietary, higher resistivity chemistry that's very different from what is used currently in the market,' Carl said. 'At present, all we can say is that it produces exceedingly good uniformity without rotation.'
In electroplating, rotation is introduced to get a uniform boundary layer and ensure that the fluid mechanics and material balance for the copper diffusion match well everywhere on the wafer. Without rotation, the Applied system produces within-wafer uniformities on the order of 1% to 1.7%. According to Carl, used without rotation, the chemistry used within a standard electroplating cell would give a uniformity of ~20%.
Applied declined to reveal more about its proprietary electrolyte, other than to say it is more environmentally friendly and easier on hardware, because it is not as corrosive as some of the standard chemicals used now.
Superfilling and High-Aspect Ratios
Superfilling is an industry goal. The concept is simple: use a standard tantalum or tantalum nitride barrier and a copper seed layer, and then plate it so that initially a good conformal seed layer is obtained. Then the superfill capability is activated, accelerating the fill inside the structure without accelerating it in the field. The result is a better fill for high-aspect ratio structures than would be otherwise obtainable with a conformal fill. Then, all that remains is plating at high current to achieve the bulk needed for CMP.
Superfilling will prolong electroplating's life as aspect ratios get higher and features go to 0.13 µm or below. This may be the transition point where CVD layers, like CVD seed and barriers, start to play a major role.
Although Applied sees no limit to the extendibility of PVD-based seed layer solutions, the fact is no one has yet come out with 0.10 µm structures to prove the point. 'We anticipate that in the 0.13 µm range copper CVD will enter mainstream applications,' Carl predicted. 'It's simple physics; at some point we're going to need something to augment the seed layer's sidewall thickness.'
Aspect ratios are the gating factor. The PVD process distributes the desired field thickness uniformly along a three-dimensional surface. When aspect ratios reach 6:1 or 7:1, conditions will have arrived at only a couple of percentage points from theoretical step coverage. That will put a very tight process window on the electroplater. Under these conditions, sidewalls will probably have to be augmented using conformal CVD copper.
Driving Cu Implementation
Chiu Ting, president and CEO of Cu-Tek (San Jose, Calif.), is amused by how the industry has changed. 'Two years ago, we had to explain why we have to do copper, and why the approach was electroplating. Then IBM and Motorola announced they were going to copper, using electroplating. Now things have swung the other way, and everyone expects copper and electroplating to immediately come on-line. Although solid progress has been made, this is not quite exactly true.'
Ting sees technical challenges. 'Copper's still in its infancy. Two years after the original IBM announcement, implementation isn't complete. We claim that copper has lower production costs than standard aluminum etching, because first, we switch to damascene, and second, electroplating is less expensive than aluminum deposition. Cost projections are one thing, attaining them another. In two or three years, the low-cost aspects will have been realized and be so well-established that lower-tier companies, including memory, will use the technology.'
Ting is not convinced people realize what is needed for copper to become mainstream. 'First, the damascene process requires that the pattern be etched into the dielectric and be filled with copper. If the fill is imperfect, there is no damascene process. Second comes the barrier and seed layer, then copper deposition or plating. The last part is copper CMP. So far, the attention has gone to copper deposition or electroplating. The rest are just as important,' he said.
Cu-Tek views the surface upon which deposition takes place as very important. The barrier layer that has been discussed has not turned out to be a major issue. The critical problem is the perfection or imperfection of the seed layer, the surface deposited upon. 'On a via hole that is 0.25 µm across and 1 µm or more deep, the sidewall seed layer must give perfect coverage - not perfect step coverage - but perfect surface coverage,' Ting explained. 'The top can be thicker than the side or bottom, but the side and the bottom must be perfectly covered; otherwise, there's a void.'
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| Fig. 3. CVD Cu seed integrated with clean and PECVD tungsten nitride (WN) barrier. The feature size is 0.14 µm with a 9:1 aspect ratio. WN barrier is 75 Å continuous and constant thickness over the bottom 80% of the feature and 225 Å on the top. The totally conformal CVD Cu seed is 500 Å. The Cu-barrier-seed product is in development as the Genus LYNX2 CBS system, supporting extendibility beyond the 0.18 µm generation. The feature has been filled without voids using electrochemical deposition. (Source: Genus) |
EEJA America (San Jose, Calif.) is another contender in the electroplating field, offering a line of wafer plating systems. According to Yukio Kobayashi, general manager, 'The main challenge is the gap fill itself. Working at 0.25 and 0.20 µm geometries is not it. It's in the 0.13 µm and below region that we shine.' Described by an industry analyst as 'the wild card of copper electroplating,' this company is geared to become a serious competitor.
Quest for Uniformity
Tom Seidel, the CTO for Genus Inc. (Sunnyvale, Calif.), believes a key metric associated with copper electroplating is how high the aspect ratio at small feature sizes fills without voids.
'With various partners, we've filled a 9:1 aspect-ratio-feature at 0.14 µm,' Seidel said. 'We put a tungsten nitride barrier down on the top, sidewalls and bottom. On the sidewalls and bottom it is 75 Å thick and uniform everywhere. Then, working with our research partners at SUNY, Albany, we put a CVD copper seed ~500 Å thick and 100% conformal. This leaves a 300 Å wide slot in a very high-aspect ratio structure. A customer development partner, using our ECD tool, filled this 40:1 aspect ratio without voids.' Seidel said this is very encouraging, indicating process robustness (Fig. 3).
Seidel pointed out that today's 0.25 µm-design-rule copper applications are not much better than aluminum. 'Tools sets and integration sequences used right now typically result in an effective resistivity for Cu of 2.5 µohm-cm, only halfway between Al and Cu. Thick barriers use up too much area of the interconnect cross-section. Even the current processes are made with tapered vias, a practice that limits scaling. As barriers get thinner, scaling is enabled,' he said.
Seidel agreed that many tools are going out broadly for development, as well as some for pilot manufacturing using Cu and SiO2. But there is a parallel focus in the development of low-k dielectrics integrated with Cu. Greater performance benefits in power and speed will come with the development of low-k and Cu. Then a second tool generation will ramp up several years from now.
Since integration compatibility with low-k and even the selection of a low-k is some time off, Seidel said the real advantage in device performance will happen at 0.15 and 0.13 µm-design-rules. 'This is bad news for tool producers, because it means there will be no volume until then, and that's a few years out yet.'
Breaking the Diffusion Barrier
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On-line Analysis of Organic Additives in Damascene Copper Processes Gene Chalyt and Peter Bratin, The use of electroplated copper for on-chip metalization in ULSI devices is gaining momentum because of the process' low cost and high throughput. Electroplated lines and trenches with sub-micron dimensions, however, are strongly affected by changes in the composition of the plating solution, requiring control techniques. The most dynamic ingredients of electroplating solutions are organic additives. Even a small imbalance between components of the additive system can cause defects in the filling of the trenches and properties of the electroplated copper. On-line monitoring and control of these additive components is therefore desirable. Cyclic Voltammetric Stripping (CVS) analysis has long been used for just such a purpose in the manufacturing of printed circuits. The same technique is now being implemented for the damascene process. While most printed wire and board manufacturers use bench-top lab analyzers, the requirements of the semiconductor industry are more demanding. The small plating cell size creates very dynamic changes in chemical component activity, which when combined with a narrow operating window generate demand for continuous, on-line, closed-loop analytical systems. Other requirements adding to the value of on-line units are high frequency of analysis, sample size limitation, cleanroom requirements and automation concerns. On-line acid copper bath controllers can meet these requirements. A bath controller samples multiple plating tanks as well as standard solution and can present results in eight different report formats. The accuracy and reproducibility of on-line analysis is significantly better than lab instruments because of temperature control, automatic calibration, reproducible conditioning and the elimination of human variations. With the CVS technique, the potential of the inert
electrode is cycled at a constant rate in the electroplating bath so that
a small amount of metal is alternately deposited on the electrode surface
and stripped off by anodic dissolution. The measured area under the
stripping peak is proportional to the plating rate, which strongly depends
on active concentration of plating additives (Fig. 1). A modification of
the CVS technique, Cyclic Step Voltammetric Stripping (CSVS) uses a series
of potential steps instead of the linear sweep to measure the effect of
additives. CVS and CSVS scans, combined with proprietary analytical
techniques, allow independent determination of organic (brightener and
carrier/leveler) components as well as inorganic materials, even in cases
of pre-mixed additive systems.
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Like others, Motorola's major challenge is getting good diffusion barriers to keep copper from spreading into the transistor level. A good planar diffusion barrier must cover step heights and deep trenches in the dielectric.
'We also must overcome copper CMP issues,' Monty said. 'How to take copper off the surface and leave a defect-free planar surface after cleaning off the slurry.' Monty said he sees lithography and packaging issues as well. 'Lithography dimensions must be driven down to the level required to get 50 billion vias on a chip. Then, as you develop your copper, you've got to be able to package it. Moving standard packaging techniques into ceramic and plastic carriers will require work.'
Motorola's focus is not so much on technology problems, which are generally viewed as straightforward engineering, but on making copper cheaper quickly. 'We're far along in determining how we're going to make our chips cheaper than aluminum and copper.' Monty conceded this is a challenge, because processes must be implemented in the most manufacturable, cheapest way.
'Now everything for Motorola is copper,' Monty said. 'We have 8 Meg and 4 Meg SRAM devices, all of our Power PC products. A whole line of wireless products is being designed for corporate sale to our communications enterprise sector, for the portable products, digital cellular telephones and the like. Volumes can only increase.'
Motorola is reducing its aluminum tools. 'The switchover is happening now,' Monty said. 'Our purchasing of equipment and planning for implementing photolithography tools to do the dimensions required are taking place now.'
Getting to Volume
John Chenault, executive vice president of the Metals Business Group at Novellus Systems Inc. (San Jose), said there is a problem in understanding what good performance is for copper processing. 'The availability of dual damascene structures that are aggressive - and available - to do plating on is very limited. Most of the work is being done on a via or trench, as opposed to a dual damascene-type structure. People do not know how those look put together in structures.'
The problem is there are not too many dual damascene structures below 0.18 µm. 'The most aggressive structure we've seen that can be filled is a 0.12 µm 10:1 trench,' Chenault said. 'We've seen 0.18 µm vias that can be filled at 4.5:1, 5:1 aspect ratios, and based on what we've seen, we believe plating will fill down 0.15 and 0.13 µm, although we haven't done dual damascene structures at those feature sizes.'
Novellus sees three drivers behind the move to copper: performance, lower power requirements and cost. The first market sector to adopt the technology will be that requiring performance, for example, in portable devices, where there is value in offering a laptop that operates twice as long on a set of batteries. Last will be those going to copper because of lower costs instead of performance, such as the memory manufacturers. This last move will probably take place at the 0.13 µm level.
New procedures are needed for copper interconnects, to use CMP to full advantage. Copper CMP is different from that of tungsten or other materials. Barriers and seeds and processes must be developed on PVD to avoid electromigration, get a continuous copper seed layer to pass the current through and be able to plate.
Regardless of obstacles, copper is in production, and devices are shipping daily.
The future is now. 
