Mavericks Reinterpret the Roadmap

Laura Peters, Senior Editor -- Semiconductor International, 4/1/1999

  Noticing certain departures from the SIA Roadmap, it occurred to me that semiconductor manufacturers may be distinguishing themselves in process capability as a natural result of increasing competition. For this reason, I find the most interesting aspect of the SIA Roadmap is tracking the activities of companies that don't follow it all that closely. For instance, I was recently told that a leading semiconductor manufacturer will not be using copper metalization at the 0.13 µm device generation. Apparently multilevel aluminum designs haven't run out of steam yet. Separately, an engineer from another semiconductor manufacturer commented that "you can hire a lot of designers for the cost of implementing copper." Another example: the Roadmap calls for the implementation of low-k dielectrics with k values of 2.5-3.0 in 0.18 µm devices and k of 2.0-2.5 at 0.15 µm. Most companies appear to be easing into the low-k regime more conservatively, implementing FSG or HSQ materials with k around 3.6 and 3.0, respectively at 0.18 µm. Yet, it seems more than plausible that some maverick will leapfrog the technology and implement an ultralow-k material with a k closer to 2.0 as soon as the 0.15 µm generation.

" Increasing competition is forcing a stratification among processing approaches and a greater need for risk-taking regarding processs decisions. "

Increasing industry maturity may have something to do with the different approaches to new technology that companies are taking. Particularly in the area of new technology adoption, companies are finding different ways to attain the same result with different materials, processes, designs and toolsets. Although this has always been the case, I believe that increasing competition is forcing more of a stratification among processing approaches and a greater need for risk-taking regarding processing decisions. Certainly risk management in the past where the industry was not performing device shrinks every six months and was not making major process replacements, such as the transition from deposition and etch-back to chemical mechanical polishing, was less critical. Equipment companies and materials suppliers must take an equal or greater amount of risk if they wish to remain players in their core markets, not to mention retain the foresight to begin new tool/process development in time for the next few device generations.

Development of shallow trench isolation (STI) processes is a case in point. Logic manufacturers began replacing LOCOS isolation with STI structures in the 0.35 µm generation, whereas DRAM manufacturers are adopting them at 0.18 µm. IC manufacturers are choosing different CVD tools for trench fill, different masking techniques, etching approaches and CMP platforms, processes and slurries (see article on page 69, this issue). It represents one of the many cases where you can look at a device cross-section and gain little understanding of how the company attained the result. Certainly extendibility of LOCOS designs, even with their variations, required a different level of risk management. As important as any other time in our history is maintaining the partnerships and relationships with customers to know when an approach is enabling as opposed to good or even just adequate.