Semiconductor Technology: A Retrospective
Staff -- Semiconductor International, 12/1/1998
The
year was 1978. A new fab cost $20 million. Experts concerned over the high cost
of manufacturing anticipated future joint ventures between companies, possibly
from different countries. Minimum device geometries were 2-3 mm, and probe yields
hovered around 10%. The industry was following Moore's Law, the phenomenon of
increasing industry productivity described by Intel's Gordon Moore three years
prior. Semiconductor International was making its debut with staff-written
feature articles covering leading-edge processing technology and expert predictions,
many of which proved prophetic. Following are brief outtakes from the first
several issues of SI.
- Deep UV lithography can be a practical technique when improvements in resist, lamps and aligner are made. Yasuaki Nakane, Toshiro Tsumori and Tadayosi Mifune, Sony Corp., Atsugishi, Japan, January-February 1979, p.45.
- Plasma etching is quickly becoming a very important technique for delineating patterns in metals, insulators and semiconductors in the manufacture of integrated circuits...Plasma deposition of materials such as silicon nitride and plasma cleaning are also expected to be important. Kenneth Galloway, National Bureau of Standards, Washington D.C., May 1979, p.65.
- Most of the design and testing problems can be resolved by accepting a less efficient chip...by adding functions on the chip which have no other purpose than testing...while this approach, to some extent, destroys the design objective of the smallest possible chip, it represents a practical engineering compromise. Glen Madland, Integrated Circuit Engineering, Scottsdale, Ariz., November-December 1978, p.33.
| Table 1. 1978's State-of-the-Art |
| 2.5 mm minimum feature sizes |
| 3-8 sec gate delays |
| Average of eight mask layers |
| Class 100 and 1000 cleanrooms |
|
First application of step-and-repeat aligners, widely used in mask making, to 4 in. wafers |
| Initial use of doped polysilicon gates |
| Use of laser-annealing to reduce poly resistance |
|
Minimum oxide thickness approached 100 Å. |
|
In CMOS and HMOS (high-performance scaled NMOS) devices, selective oxidation used to grow thick field oxides. |
|
Shallow source/drain, threshold adjust and field adjust implants, other doped regions formed using diffusion processes |
|
Wet etching dominated; plasma etch employed where undercutting becomes intolerable. |
Of course, industry experts of the time did not always accurately predict the future. Technologies that proved less successful than anticipated included silicon-on-sapphire substrates and GaAs, while CMOS structures, originally viewed as a high-cost alternative to scaled NMOS, were drastically underrated.
Possibly the experts' greatest error was believing that x-ray or electron-beam lithography would be essential in imaging features below 1 mm. In subsequent years this prediction was pushed out further to the 0.8 mm generation, 0.6, 0.5 and so on. Early success at deep-UV wavelengths indicated a possible transition following g-line, h-line and i-line lithography. Experts could not have expected that deep-UV technology would take 20 years to come to fruition and prove more practical than e-beam or x-ray.
State-of-the-art semiconductor processing in the late 1970s (see Table) addressed the needs of 16k RAM devices (costing $0.45/kbit) and the 8086 microprocessor from Intel (costing $1.20/transistor). A new type of memory technology, non-volatile memory, capable of storing charge in the absence of power for the first time, was just emerging. The 8086 processor was representative of the largest die size at 0.33 cm2.
Wafer processing was undergoing a variety of transitions from wet etching to plasma etching, contact and proximity printers to projection aligners, aluminum evaporation to dc magnetron sputtering, and diffusion (using solid sources, liquid doping from bubblers or spin-on dopants) to ion implantation. IC manufacturers began integrating lithography exposure tools with tracks. In packaging, users were making the transition from gang bonding to wire bonding. Assembly and packaging were undergoing a revolution in automation, from single-device processing to assembling between 10 and 30 devices on a single strip of leadframe. Manual interconnection was rapidly approaching its acceptable maximum of 64 pins per device. Equipment manufacturers began introducing dicing, die attach, wire bond/gang bond, encapsulation and seal and finishing machines that could be integrated, minimizing operator interaction and setting standards for improved quality, yield and reliability.
While prognosticators in the late 1970s were able to pinpoint key industry
trends, today's forecasters, even with the aid of the 1997 SIA Roadmap, attempt
to project expected revolutionary changes in process and device technologies
of the future, unlike the largely evolutionary changes of the past.