Twenty Years Past and Future:& Continued Scaling and New Materials Dominate
Peter Singer, Editor-in-Chief -- Semiconductor International, 12/1/1998
In this, our 20th anniversary issue, we are looking back over the last 20 years to see how technology has changed and also attempting to look forward to anticipate what the next 20 years might bring.
In the field of wafer processing which we define to include ion implant, thermal processing, etch, CVD, sputtering, CMP and electroplating enormous strides have been made over the last 20 years. Indeed, chemical mechanical polishing (CMP) was not even used even 10 years ago, and electroplating has only been accepted as a viable process within the last two years. We have also seen the introduction of a variety of new materials, including copper and low dielectric constant insulators (low-k dielectrics), tantalum, and, in the case of memories, platinum and high dielectric constant materials. Silicon-on-insulator (SOI) substrates have become more mainstream, and silicon germanium devices appear poised to take off.
Most wafer processing advances over the last 20 years have been driven by scaling, and this is likely to continue for the next 20 years. In the early eighties, leading-edge devices had features of several microns. Today, 0.25 µm (250 nm) devices are in production and a well defined roadmap shows us reaching 0.05 µm (50 nm) minimum geometries by 2012. Extrapolate that a bit further, and you'll see we should be reaching 10 nm around 2018-19.
Substrate diameter is also on the increase. Twenty years ago, 4 and 5 in. wafers were standard. That progressed to 6 in. and then 8 in. Now, work is underway on 12 in. (300 mm), which is likely to be in production within four to five years. The SIA roadmap predicts that 450 mm wafers will come into play around 2009.
Scaling has also resulted in significant increases in device complexity, most notably the number of interconnect levels. Twenty years ago, two or three levels of interconnects were standard. Today, leading edge devices have six or seven, and this could increase to 10 or more over the next 20 years. One of the main drivers in the push to a copper/low-k approach over the traditional aluminum/SiO2 interconnect scheme is to minimize the number of interconnect levels. Already, companies such as IBM and Motorola have put copper into production, and a combined copper/low-k approach is probably not far off. The first few generations of copper will employ a sputtered Cu seed layer, and electroplating will be used for plug fill and main interconnect formation. In subsequent generations, as dimensions shrink, the seed layer will probably be deposited by CVD, and eventually electroplating will be replaced by CVD as well due to the difficulty in filling narrow, high aspect ratio holes. Copper interconnects will almost certainly be patterned with a dual damascene approach, where holes and trenches are cut into a planar oxide and then filled with metal. This means two of today's most challenging processes metal etch and dielectric gap fill will simply go away. Diffusion barriers will play an increasingly important role, since they must be thin to minimize the resistance of the overall plug but still thick enough to act as an efficient barrier against diffusion. Some suspect ternary compounds (TiSiN) may be the answer but more research is needed.
In what some call the front end of the line (FEOL) which encompasses the formation of the transistors' source and drain regions, gate dielectric and gate there have not been many radical changes over the last 20 years. Doping is still done with mass separated ion implantation; the gate dielectric is still a thermally grown oxide and the gate itself is a highly doped polysilicon. In recent years, the biggest challenge has been to form the ultra-shallow junction of the p-channel transistors, leading to small fairly radical changes in ion implant technology to enable implant energies well below 5 keV.
Over the next 20 years, we will likely see renewed interest in raised source/drains and alternative doping schemes such as PLAD (Plasma Assisted Doping) and GILD (Gas Immersion Laser Doping), which eliminate the need for huge and expensive ion implanters. We will also see interest in using high-k dielectrics as an alternative to thermally grown gate oxides, as gate dielectric thickness drops to below 10Å. There is also interest in going to away from a highly doped poly gate to a metal gate.
Beyond that, cost of ownership will remain a constant concern. 
