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Emerging Technologies: 1978

Ruth DeJule, Associate Editor -- Semiconductor International, 12/1/1998

Twenty years ago, the semiconductor industry was booming. Along with GaAs, silicon-on-insulator (SOI) was an emerging technology; 4 in. wafers were being introduced, and the 8080 microprocessor, EPROM flash memory, SRAM and piggybacked 16Kb DRAMs were breaking into the commercial market. A baseline process for 64Kb DRAMs was underway, while a 256Kb process was being developed. A far cry from the 32 bit Pentium with multi gigabite address space and package pincounts on the order of hundreds, concerns surrounded microprocessors at 1978's ISSCC. Would the industry be able to meet the demand for data paths greater than 8 bits, an address space greater than 64KB, provide a package with more than 40 pins, and would technology be in place to put 20,000-50,000 transistors on a single chip without melting?

Considered an emerging technology in the 1970s, 16Kb CCD memories ultimately could not compete with 4Kb DRAMs, though later they would be used as image sensors. Similarly, magnetic bubble memory technology, a combination of semiconductor and magnetic memory technologies, was anticipated to compete with rotating magnetic disk memory (hard and floppy drives). Twenty years later, we've seen how DRAM and magnetic disk drive memory have changed the world.

Today's emerging technologies are driven by Moore's Law, particularly with the recent prospect of three-level memory and logic instead of two, and system on a chip (SOC) with combinations of CPU, I/O, microprocessor, EPROM, SRAM and DRAM (main memory) on a single chip (see Figure). Will this occur at a competitive cost? What about replacement costs and upgrade capabilities? asked SEMATECH's Tim Marbeiter. These remain to be seen.

12ETECHI
The next 20 years may see a change from well-defined device families to a split, dividing the device stream into two branches, one predominantly memory and the other system on a chip. (Source: Kopp Semiconductor Engineering)
Recent years have seen a renewed interest in the insulating properties of SOI wafers to enhance device performance. Though, according to Dr. Robert Kopp, there is some theoretical support that bulk silicon will still be a viable wafer material out to 4 terabit and 25 nm gate lengths. An extrapolation of the SIA roadmap places 25 nm design rules 20 years out to 2018. At this point, it's been suggested, we may have reached the practical limit of MOS transistor technology as we know it today. At a time when the industry is accelerating feature size shrinks, the length of time to absorb a replacement technology is shortening. Though manufacturing costs and complexity may slow this approach, perhaps a slowdown in Moore's law is called for, ventured Ron Dornseif, principal analyst at Dataquest. In addition to foundries and highly standardized process modules, what may be emerging is a change in philosophy.

In the past 20 years, the demand for low cost electronic function has been insatiable, and therefore the ability to supply electronic components determined the pace of technology development. The SIA Roadmap was set as a benchmark, and by its very existence, a company had to keep pace to be competitive. Particularly in the PC arena and to a lesser extent in telecommunications, there appears to be a slowdown in demand. The PC world is the most mature and seems to be moving toward becoming a commodity, which means low cost, high volume. At the same time, semiconductors are now beginning to focus on SOC, yet the Roadmap is focused on the microprocessor and DRAM. SOC can mean many different designs, each at low volume and high cost. The question begging to be asked: Should Moore's Law be allowed to respond to these market dynamics?

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