Copper Migration Following Different Paths

-- Semiconductor International, 3/1/1999

Copper interconnect technology adoption just started within the past year, and the technology is already taking a strong hold in some places. Companies are taking different approaches to implementing it into their products. Some have implemented copper at every metal level; some are putting it on the top two levels, and some are putting it off to the next technology generation.

The 1999 National Technol ogy Roadmap for Semiconductors indicated this as a probable migration. Under the heading Metal Potential Solutions, it states, 'Aluminum alloy-based interconnect will continue to play a substantial role as the interconnect metal for at least 10 more years. The introduction of Cu will be in phases for some manufacturers, with the upper (fat) wiring levels first converted to Cu to accommodate the high current of those levels.'

The first of copper's advantages comes on the larger traces for handling higher currents and reliably distributing power. The higher conductivity also provides a big advantage in reducing clock skew across the chip.

Some companies are putting copper interconnnects on top layers and aluminum on lower layers. (Source: Mitsubishi Electric Corp.)

Mitsubishi (Tokyo) recently announced plans to use copper for the top two metal layers of a six-layer process, while using aluminum for the remaining layers (see Figure). The company found that the combination of copper and its silicon nitride diffusion barrier gave no net conductivity advantage over aluminum and its diffusion barrier for small interconnect traces. It found that for larger traces it did provide an advantage. Mitsubishi engineers presented results of their study at the IEDM conference in December. The company uses a dual damascene process for the copper layers. It plans to use this approach for 180 nm (0.18 µm) processes and expects it to be viable down to 150 nm (0.15 µm) processes.

VLSI Technology recently announced its VSC11 process. It is a 150 nm five-layer, aluminum-based process that offers copper as an option for the top two layers. The company serves a number of very cost sensitive markets, and its position is that using copper could make devices for those markets too expensive. The company is offering the mixed solution for applications requiring more performance. With this approach, VLSI plans to learn as much as possible about copper processing before committing to an all-copper process. The company plans to use proven tungsten plug technology on all metal layers for the present.

Last September, Lucent Technologies announced its COM-2 technology, which is all aluminum at this time. At that time, Mark Pinto, chief technical officer of Lucent's microelectronics group said, '... we will introduce copper interconnects into our modular COM-2 process at the point when it provides cost-effective performance advantages for our customers. Despite the hype, the market is not demanding copper, and equivalent performance can be achieved in this timeframe by more cost-effective approaches.'

Intel (Santa Clara, Calif.) has chosen to forego copper interconnects for the 180 nm technology generation. The company announced several months ago that it will stay with aluminum and use increased aspect ratios. This will keep metal traces farther apart, reducing capacitive coupling. Intel plans to start using copper in its 130 nm (0.13 µm) technology in the 2001-2002 time frame.

Motorola Semiconductor Products Sector (Austin, Texas) produced a SRAM product last year using a 0.20 µm design. It used a dual damascene copper process for all interconnects except for a tungsten contact to the silicon. The company plans to migrate copper to all products over the next five years.

IBM announced last September that it was shipping 400 MHz PowerPC 740/750 chips with copper interconnects and that plans were in place to use it in more products this year. The process, CMOS 7SF, is a 180 nm technology.

Another option for copper migration that has gone relatively unnoticed is to push the top metal layers onto the package. Some memory manufacturers have tried this approach with promising results. Tessera (San Jose, Calif.) has been pushing the idea as a cost-effective way to migrate to copper, and it has uncovered some other advantages. The company's packaging technology puts a compliant layer between the die and the package. This allows the use of large power planes and clock tree structures in the package that would break if they were put on the die due to copper's coefficient of thermal expansion (CTE) difference with silicon.

Though copper adoption is taking hold, it will be several years before it is pervasive. In most cases, demand and cost-effectiveness considerations are dictating companies' migration paths.